Systolic Architecture Research Articles

Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2

This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic architectures result in parallelized, DSP48E2-optimized scheduling of operations analogous to the FIOS block variant of the Montgomery Multiplication. We explore the impacts of different pipelining strategies within DSP blocks, scheduling of operations, processing element configurations, global design structures and their tradeoffs in terms of performance and resource costs. We discuss the application of our methodology to multiple types of DSP primitives. We provide ready-to-use fast, efficient, and fully parametrizable designs, which can adapt to a wide range of requirements and applications. Implementations are scalable to any operand width. Our most efficient designs can perform 128, 256, 512, 1024, 2048, and 4096 bits Montgomery modular multiplications in 0.0992 μs, 0.2032 μs, 0.3952 μs, 0.7792μs, 1.550 μs, and 3.099 μs using 4, 6, 11, 21, 41, and 82 DSP blocks, respectively.

Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

The brain’s connectivity is locally dense and globally sparse, forming a small-world graph—a principle prevalent in the evolution of various species, suggesting a universal solution for efficient information routing. However, current artificial neural network circuit architectures do not fully embrace small-world neural network models. Here, we present the neuromorphic Mosaic: a non-von Neumann systolic architecture employing distributed memristors for in-memory computing and in-memory routing, efficiently implementing small-world graph topologies for Spiking Neural Networks (SNNs). We’ve designed, fabricated, and experimentally demonstrated the Mosaic’s building blocks, using integrated memristors with 130 nm CMOS technology. We show that thanks to enforcing locality in the connectivity, routing efficiency of Mosaic is at least one order of magnitude higher than other SNN hardware platforms. This is while Mosaic achieves a competitive accuracy in a variety of edge benchmarks. Mosaic offers a scalable approach for edge systems based on distributed spike-based computing and in-memory routing.

Efficient enhanced Recursive Least Square algorithm adaptive filtering scheme for artifacts removal in ECG signals

This paper proposes an improved Recursive Least Square (RLS) algorithm to address the limitations of the conventional RLS algorithm, which suffers from poor performance when dealing with non-stationary noise. The proposed algorithm, along with various algorithms, have been designed using Xilinx System Generator (XSG). These algorithms have been tested to denoise ECG signals that have been corrupted with four types of real noise obtained from the MIT-BIH dataset. The improved algorithm utilizes a systolic architecture that enables faster processing and better noise reduction capabilities. The experimental results demonstrate that the proposed algorithm with and without systolic architecture outperforms the conventional RLS algorithm and other state-of-the-art algorithms in terms of signal-to-noise ratio (SNR), mean squared error (MSE), and convergence speed.

Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor

With the growing demand for processing deep learning applications on edge devices, on-device DNN training has become a major workload to execute a variety of vision tasks suited for users. Therefore, architectures employed with algorithm co-design to accelerate the training process have been steadily studied. However, previous solutions are mostly supported by extended versions of the inference studies, such as sparsity, data flow, quantization, etc. Moreover, most works examine their schemes on from-the-scratch training that cannot tolerate inaccurate computing. Accordingly, there are still factors that hinder the overall speed of the DNN training process that has not been addressed in practical workloads. In this work, we propose a runtime convergence monitor to achieve massive computational savings in the practical on-device training workloads (i.e., transfer learning-based task adaptation). By monitoring the network output data, we determine the training intensity of incoming tasks and adaptively detect the convergence in iteration intervals for training diverse datasets. Furthermore, we enable computation skip of converged images determined by the monitored prediction probability to enhance the training speed within an iteration. As a result, we perform an accurate but fast convergence in model training for the task adaptation with minimal overhead. Unlike the previous approximation methods, our monitoring system enables runtime optimization and can be easily applicable to any type of accelerator attaining significant speedup. Evaluation results on various datasets show geomean of 2.2× speedup when applied in any systolic architectures and further enhancement of 3.6× when applied in accelerators dedicated for on-device training.

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

In this paper, we present a dynamically reconfigurable hardware accelerator called FADES (Fused Architecture for DEnse and Sparse matrices). The FADES design offers multiple configuration options that trade off parallelism and complexity using a dataflow model to create four stages that read, compute, scale and write results. FADES is mapped to the programmable logic (PL) and integrated with the TensorFlow Lite inference engine running on the processing system (PS) of a heterogeneous SoC device. The accelerator is used to compute the tensor operations, while the dynamically reconfigurable approach can be used to switch precision between int8 and float modes. This dynamic reconfiguration enables better performance by allowing more cores to be mapped to the resource-constrained device and lower power consumption compared with supporting both arithmetic precisions simultaneously. We compare the proposed hardware with a high-performance systolic architecture for dense matrices obtaining 25% better performance in dense mode with half the DSP blocks in the same technology. In sparse mode, we show that the core can outperform dense mode even at low sparsity levels, and a single-core achieves up to 20x acceleration over the software-optimized NEON RUY library.

Improving Security of Internet of Vehicles Based on Post-quantum Signatures with Systolic Divisions

Internet of Things (IoT) techniques have been employed in many areas, e.g., vehicles, smart home, and medicine. Among the applications of IoTs, the Internet of Vehicles (IoV) is one of the most popular techniques. IoVs are protected by public key cryptographic systems, such as RSA and ECC. However, such systems are vulnerable to quantum computer attacks. Thus, we improve the security of IoV-based post-quantum signatures, which can resist quantum computer attacks. The key operations are divisions in a finite field. Hence, we improve the security of IoV-based post-quantum signatures with division by employing systolic architectures. We propose a systolic architecture for computing division in composite fields. After that, we improve the IoT security-based post-quantum signatures with systolic divisions. We test and verify our design on a Field-Programmable Gate Array (FPGA); the experimental results confirm our estimates. Furthermore, the optimized method proposed can be further applied to various applications like solving system of linear equations and cryptographic applications for IoT security.

Design of Digital FIR Filter with Systolic Architecture using Reversible Logic Gates

The design of Digital filters plays a prominent role in the present scenario. The delay and area are the two major components that need to be concentrated on. The delay tap present in FIR filters should be suppressed to inflate the speed of the system. In this paper, the FIR filter design using systolic architecture with associative technique is implemented. This system includes a number of identical elements that are interconnected one after another by programmed manner to get the specified output. Here the proposed systolic FIR is compared with TDA logic block using bisection technique. There will be a greater reduce of critical path using the systolic architecture. To intensify the speed and to truncate the system delay the processing elements such as adders, multipliers and delay elements are designed by reversible logic operations. The proposed filter is better in many aspects such as density of gates, power consumption and delay outputs compared with existing filter. Experimental results are performed using the Xilinx ISE tool.

MOZART+: Masking Outputs With Zeros for Improved Architectural Robustness and Testing of DNN Accelerators

Deep Neural Networks (DNNs) are increasingly used in safety critical autonomous systems. We present MOZART+, a DNN accelerator architecture which provides fault detection and fault tolerance. MOZART+ is a systolic architecture based on the Output Stationary (OS) data-flow, as it is a data-flow that inherently limits fault propagation. In addition, MOZART+ achieves fault detection with on-line functional testing of the Processing Elements (PEs). Faulty PEs are swiftly taken off-line with minimal classification impact. We show how to handle the case of layers with a small number of neurons. The implementation of our approach on Squeezenet results in a loss of accuracy of less than 3% in the presence of a single faulty PE, compared to 15-33% without mitigation. The area overhead for the test logic does not exceed 8%. Dropout during training further improves fault tolerance, without a priori knowledge of the faults. We present a detailed fault-injection study on multiple systolic architectures, considering different fault-models and comparing different measures of accuracy.

FPGA-based systolic deconvolution architecture for upsampling

A deconvolution accelerator is proposed to upsample n × n input to 2n × 2n output by convolving with a k × k kernel. Its architecture avoids the need for insertion and padding of zeros and thus eliminates the redundant computations to achieve high resource efficiency with reduced number of multipliers and adders. The architecture is systolic and governed by a reference clock, enabling the sequential placement of the module to represent a pipelined decoder framework. The proposed accelerator is implemented on a Xilinx XC7Z020 platform, and achieves a performance of 3.641 giga operations per second (GOPS) with resource efficiency of 0.135 GOPS/DSP for upsampling 32 × 32 input to 256 × 256 output using a 3 × 3 kernel at 200 MHz. Furthermore, its high peak signal to noise ratio of almost 80 dB illustrates that the upsampled outputs of the bit truncated accelerator are comparable to IEEE double precision results.

S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks

Convolutional neural networks (CNNs) have achieved great success in performing cognitive tasks. However, execution of CNNs requires a large amount of computing resources and generates heavy memory traffic, which impose a severe challenge on computing system design. Through optimizing parallel executions and data reuse in convolution, systolic architecture demonstrates great advantages in accelerating CNN computations. However, regular internal data transmission path in traditional systolic architecture prevents the systolic architecture from completely leveraging the benefits introduced by neural network sparsity.Deployment of fine-grained sparsity on the existing systolic architectures is greatly hindered by the incurred computational overheads.In this work, we propose S2Engine a novel systolic architecture that can fully exploit the sparsity in CNNs with maximized data reuse. S2Engine transmits compressed data internally and allows each processing element to dynamically select an aligned data from the compressed dataflow in convolution. Compared to the naive systolic array, S2Engine achieves about 3.2 and about 3.0 improvements on speed and power efficiency, respectively.

VLSI Systolic Architecture Implementation for Noise Elimination from ECG Signal

Different forms of noise are caused by electrocardiogram (ECG) signals, which vary founded on frequency content. To enhance accurateness and dependability, the elimination of such a trouble is necessary. Denoising ECG pointers is difficult as it is difficult to add secure coefficient filter. It is possible to use adaptive filtering techniques, in which the feature vectors can be changed to top dynamic signal changes. With a degree of sparsity, such as non-sparse, partial sparse and sparse, the framework shifts. The Least Mean Square (LMS) and Zero Attractor LMS (ZA-LMS) convex filtering combination is ideal for both Sparse and Non-Sparse settings. Popular the proposed design, the Systolic Architecture is introduced in direction to improve device efficiency and to reduce the combinational delay path. Systolic architectures are developed using the Xilinx device generator tool for normal Least Mean Square (LMS), Zero Attractor LMS (ZA-LMS) and Convex combinations of Least Mean Square (LMS) and Zero Attractor LMS (ZA-LMS) interfaces.Simulation remains performed with various ECG signals obtained from MIT-BIH database as input to designed filtering and its SNR is obtained. The study shows that the SNR value in systolic architectures is higher than in filter bank structures. For systolic LMS buffers, the SNR value is 4.5 percent greater than the structure of the Lms algorithm. The SNR for the systolic separation technology of ZA-LMS is 2.5 percent higher than the separation technology of ZA-LMS. The SNR value for LMS and ZA-LMS filtering structure systolic convex combinations is 6% higher than that for LMS and ZA-LMS filtering structure convex combinations.

Comparison of Swarm Optimization and Memetic Algorithm for Systolic Mapping of Texture Analysis

Systolic processors offer a hardware design which can accommodate more functions in a small footprint. Hardware utilization efficiency can be enhanced by appropriately designating the intended hardware with a task in space and time through parallel computing platforms. Regular algorithms known for their computational complexity can be mapped to systolic array by dependence graphs, which allot hardware to the design data. Manual mapping techniques tend to be tedious with more inaccuracy and calls for efficient mapping techniques, automated through algorithmic procedures. Texture Analysis marks the preliminary progression of image analysis and interpretation. Automotive systems, Robotics, Industrial processing and similar automated applications can be simplified through texture analysis. This work deals with employing evolutionary algorithms for mapping texture analysis onto systolic architecture. Memetic Algorithms (MA) and Particle Swarm Optimization (PSO) algorithms were comparatively studied and the efficiency of designing a parallel architecture through systolic array is analyzed through cost function and processing time.

High performance hardware design of compressor adder in DA based FIR filters for hearing aids

Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the different types of hearing loss, it is necessary to selectively amplify sounds at required frequencies. The main aim of the hearing aid is to selectively remove the noise signal such that the processed sound matches ones audiogram. To achieve this, the decimation filter in hearing aids can be design using multiplier less architecture which should be able to adjust sound levels at arbitrary frequencies within a given spectrum. In hearing aids, decimation filter plays a key role. This paper presents a low complexity design of a digital finite impulse response (FIR) filter for digital hearing aid application. This paper proposed approximate 4:2 compressor adders in memory less DA based FIR filter architecture. In DA architecture the area of the ROM increases gradually when filter order is increased. Memory less DA is designed using compressor adders is a solution to decrease the power consumption and area of the FIR filters and makes the area and power reduction for hearing aid application. The proposed DA based FIR filter architecture is synthesized on 90 nm technology using Synapsis Application Specific Integrated circuit design compiler. The proposed architecture has 45% reduction in area delay product when distinguish with systolic architecture and 10% less ADP when compare with OBC DA architecture. The proposed design is also implemented Field Programmable Gate Array and the results shows that the proposed architecture has less slices than best existing designs. The proposed architecture is used in decimation filter of hearing aids applications using matlab simulink, which removes the unwanted signal.

Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

SAPTM: Towards High-Throughput Per-Flow Traffic Measurement with a Systolic Array-Like Architecture on FPGA

Per-flow traffic measurement has emerged as a critical but challenging task in data centers in recent years in the face of massive network traffic. Many approximate methods have been proposed to resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is the sketch-based method. However, sketches are affected by their high computational cost and low throughput; moreover, their measurement accuracy is hard to guarantee under the conditions of changing network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely deployed in data centers, as they demonstrate a good fit for high-speed network processing. In this work, we aim to address the problem of per-flow traffic measurement from a hardware architecture perspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput per-flow traffic measurement on FPGA. We adopt memory-friendly D-left hashing in the design of SAPTM, which guarantees high space utilization during flow insertion and eviction, successfully addressing the challenge of tracking a high-speed data stream under limited memory resources on FPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that SAPTM possesses high space utilization. Comparisons with state-of-the-art sketch-based solutions show that SAPTM outperforms comparison methods in terms of throughput by a factor of 14.1x–70.5x without any accuracy loss.

Generating Systolic Array Accelerators With Reusable Blocks

Systolic array architecture is widely used in spatial hardware and well-suited for many tensor processing algorithms. Many systolic array architectures are implemented with high-level synthesis (HLS) design flow. However, existing HLS tools do not favor of modular and reusable design, which brings inefficiency for design iteration. In this article, we analyze the systolic array design space, and identify the common structures of different systolic dataflows. We build hardware module templates using Chisel infrastructure, which can be reused for different dataflows and computation algorithms. This remarkably improves the productivity for the development and optimization of systolic architecture. We further build a systolic array generator that transforms the tensor algorithm definition to a complete systolic hardware architecture. Experiments show that we can implement systolic array designs for different applications and dataflows with little engineering effort, and the performance throughput outperforms HLS designs.

High-throughput area-delay-efficient systolic multiplier over GF(2m) for a class of trinomials

The paradigm of Edge Computing in Internet of Things (IoT) demands high-throughput implementations of IoT edge devices. Security algorithms used in these devices heavily use GF(2m) multiplications. Systolic structures for GF(2m) multipliers can offer high throughput rates along with other features such as regularity, concurrency, and modularity. Many systolic architectures for GF(2m) multiplier were proposed in the literature to achieve low area and time complexities. In this paper, we propose a high-throughput and low area-delay complexity systolic structure for the hardware realization of polynomial basis multiplication in GF(2m) for a class of trinomials. The complexity analysis shows that the proposed architecture results in achieving high throughput and less area-delay complexity compared with the existing polynomial basis multipliers in the literature. When compared with the best available multipliers, the multiplier realized using the proposed architecture achieves throughput improvement by 42% and reduction in area-delay product by 7% for m=409. Application specific integrated circuit (ASIC) implementations of the proposed multiplier and the best available multipliers confirm that the proposed multiplier outperforms the other multipliers. Hence, the proposed high-throughput area-delay-efficient multiplier can be employed in IoT edge devices.

Algorithm for Computation of DCT and its Implementation using a Systolic Architecture

In this paper a new algorithm for computing N-point DCT, where N=4r, r>1 is presented. A new algorithm has been derived that can compute the 1D DCT and it is realized in systolic array that utilizes identical processing elements (PE’s). The proposed approach can be used to obtain other transform like Discrete Sine Transform (DST), Discrete Hartley Transform (DHT). The suggested algorithm requires reduced number of multiplications as compared to the other methods of computing DCT. This suggests structure meets the architectural challenge and it is simple, regular design and cost-effective for special-purpose system.

Algorithm for Computation of DCT and its Implementation using a Systolic Architecture

Algorithm for Computation of DCT and its Implementation using a Systolic Architecture

Swallow: A Versatile Accelerator for Sparse Neural Networks

Sparse neural networks (SNNs) are emerging as a promising technique for resource-limited intelligent embedded systems because of the compact model size and the uncompromised accuracy. Recently, most of the dedicated neural network accelerators are beginning to exploit the sparsity of neural network models for performance boost and energy saving. However, existing sparsity-aware accelerators fail to support both sparse weights and activations in neural networks or support them at the same time for both convolutional (Conv) layers and fully connected (FC) layers, which dominate the computational time of neural networks. In this article, we propose a novel sparsity-aware accelerator architecture, called Swallow, to sufficiently improve the inference performance by eliminating ineffectual weights and activations of neural networks. Swallow comprises: 1) a 2-D systolic architecture that fully utilizes the sparsity of both weights and activations in both Conv and FC layers and 2) a sparsity-aware dataflow which is optimized to reuse both weights and activations and to achieve high processing element (PE) utilization by sparse matrix multiplication tiling. Comprehensive evaluations based on a place-and-route process show that Swallow, with 614 GOP/s peak performance and 1.26-W power, outperforms a state-of-the-art sparsity-aware accelerator Cambricon-X by $1.32\times $ in term of energy efficiency.