System-on-package Research Articles

A compact LTCC Bluetooth system module with an integrated antenna

In this article, a system-on-package (SoP) approach for Bluetooth system module applications using low-temperature co-fired ceramic (LTCC) technology is presented. The developed LTCC integrated substrate for our Bluetooth module application is overall 12 × 12 × 1 mm3 in size, with integration of two originally proposed components, a balanced-to-unbalanced bandpass filter and a folded meander-line inverted-F antenna, as well as other passive circuitries. The embedded balanced-to-unbalanced filter, which is derived from the basic center-tapped transformer circuit, works simultaneously as a balun and a bandpass filter, thus leading to a significant amount of size reduction for the overall module. Likewise, comparing to the usual quarter-wavelength inverted-F antennas, our proposed antenna is only one-tenth of a wavelength in length—but no sacrificing of antenna efficiency. Consequently, couplings among different functional blocks of this highly integrated module are crucial to its performance and the resulting effects are discussed. A fully functional prototype is successfully fabricated and tested, demonstrating a promising solution for Bluetooth applications. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.

CMOS-Compatible Through Silicon Vias for 3D Process Integration

ABSTRACTAs the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.

A BARIUM ZIRCONATE TITANATE-BASED INORGANIC DIELECTRIC MATERIAL WITH HIGH PERMITTIVITY AS A LEAD-FREE INSULATOR FOR SEMICONDUCTOR APPLICATIONS

ABSTRACT BaZr x Ti1−x O3-Ba(Fe0.5Ta0.5)O3-FeTaO4(BZT-BFT-FT) ceramics were fabricated by a columbite route in an attempt to develop a lead-free inorganic dielectric material suitable for use as an insulating material with high relative permittivity and low dielectric loss for next-generation system-on-package (SOP) applications. The fabricated BZT ceramics with compositions of BaZr x Ti1−x O3 with x = 0.05–0.30 all had a single-phase perovskite structure. The sample with 20/80 composition (100x /(100–100x)) in BaZr( x Ti1−x O3) exhibited the best dielectric properties with an ideal Curie temperature of 30°C, high relative permittivity of 4750, and low dielectric loss of 0.6% at 1 MHz. The addition of BFT as a depressor agent and FT as a sintering aid, at optimal concentrations of y = 0.03 ((1–y)BZT-yBFT) and 0.5 mass% FT, yielded ceramics with ϵr of 3080 and tanδ of 0.05% at 1 MHz. This novel lead-free inorganic dielectric material can therefore be expected to be useful as an inorganic insulating material with high permittivity for SOP applications.

A BARIUM ZIRCONATE TITANATE-BASED INORGANIC DIELECTRIC MATERIAL WITH HIGH PERMITTIVITY AS A LEAD-FREE INSULATOR FOR SEMICONDUCTOR APPLICATIONS

ABSTRACT BaZr x Ti1 − x O3-Ba(Fe0.5Ta0.5)O3-FeTaO4 (BZT-BFT-FT) ceramics were fabricated by a columbite route in an attempt to develop a lead-free inorganic dielectric material suitable for use as an insulating material with high relative permittivity and low dielectric loss for next-generation system-on-package (SOP) applications. The fabricated BZT ceramics with compositions of BaZr x Ti1 − x O3 with x = 0.05–0.30 all had a single-phase perovskite structure. The sample with 20/80 composition (100x/(100−100x) in BaZr x Ti1 − x O3) exhibited the best dielectric properties with an ideal Curie temperature of 30°C, high relative permittivity of 4750, and low dielectric loss of 0.6% at 1 MHz. The addition of BFT as a depressor agent and FT as a sintering aid, at optimal concentrations of y = 0.03 ((1−y)BZT-yBFT) and 0.5 mass% FT, yielded ceramics with ϵr of 3080 and tanδ of 0.05% at 1 MHz. This novel lead-free inorganic dielectric material can therefore be expected to be useful as an inorganic insulating material with high permittivity for SOP applications.

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous technologies and to support robust manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density I/O interconnection can enable tight integration of heterogeneous technologies which approximate the performance of an integrated system-on-chip with a virtual chip using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density microbump interconnections scale to smaller size. In addition to heterogeneous integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Physical Design for 3D System on Package

The SoC paradigm is a system integration approach that integrates large numbers of transistors as well as various mixed-signal active and passive components onto a single chip. This realization-led to the 3D system-in-package (SiP) approach, alternatively called 3D ICs or 3D stacked die/package. Designers can take SiP a step further by embedding both active and passive components, but passive-component embedding is bulky and requires thick-film discrete components. Thick-film component embedding distinguishes SiP from system on package (SoP), an emerging 3D system integration concept that involves embedding both active and passive components. SoP, however, incorporates ultrathin films at microscale to embed the passive components, and the package rather than the board is the system. SoP overcomes both the computing and integration limitations of SoC, SiP, multichip modules (MCMs), and traditional system packaging by having global wiring as well as RF, digital, and optical component integration in the package instead of on the chip. Moreover, 3D SoP addresses the wire delay problem by enabling the replacement of long, slow global interconnects with short, fast vertical routes.

Highly integrated millimeter-wave passive components using 3-D LTCC system-on-package (SOP) technology

In this paper, we demonstrate the development of advanced three-dimensional (3-D) low-temperature co-fired ceramic (LTCC) system-on-package (SOP) passive components for compact low-cost millimeter-wave wireless front-end modules. Numerous miniaturized easy-to-design passive circuits that can be used as critical building blocks for millimeter-wave SOP modules have hereby been realized with high-performance and high-integration potential. One miniaturized slotted-patch resonator has been designed by the optimal use of vertical coupling mechanism and transverse cuts and has been utilized to realize compact duplexers (39.8/59 GHz) and three- and five-pole bandpass filters by the novel 3-D (vertical and parallel) deployment of single-mode patch resonators. Measured results agree very well with the simulated data. One multiplexing filter, called the directional channel-separation filter, that can also be used in mixer applications shows insertion loss of <3 dB over the bandpass frequency band and a rejection /spl sim/25 dB at around 38.5 GHz over the band-rejection section. LTCC fabrication limitations have been overcome by using vertical coupling mechanisms to satisfy millimeter-wave design requirements. Lastly, a double-fed cross-shaped microstrip antenna has been designed for the purpose of doubling the data throughput by means of a dual-polarized wireless channel, covering the band between 59-64 GHz. This antenna can be easily integrated into a wireless millimeter-wave link system.

A 60-GHz multilayer parasitic microstrip array antenna on LTCC substrate for system-on-package

This letter describes a compact and high-gain multilayer parasitic microstrip array antenna (MPMAA). The design and performance of the proposed array antenna are presented. The antenna employs three layers with a 2/spl times/2 parasitic array on each layer. The developed prototype MPMAA employs a multilayer low-temperature co-fired ceramic (LTCC) substrate that is well suited to the assembly of MMIC chips. The fabricated MPMAA achieves a 7.17 dBi absolute gain at 60 GHz including the loss derived from the feeding parts and RF probe to measure its antenna performance. The spacing of the top layer of the parasitic array constructed by 2/spl times/2 elements has a free-space wavelength of 0.36 and the chip size is 10 mm/sup 2/. The fabricated MPMAA achieves both compact and high directional gain and satisfies the requirements for a millimeter-wave system-on-package (SOP).

Warpage-induced lithographic limitations of FR-4 and the need for novel board materials for future microvia and global interconnect needs

The effect of warpage on lithographic capabilities of organic circuit boards with multilayered thin film buildup was investigated. Two to six epoxy layers were built on various candidate boards to characterize the warpage and correlate it with analytical models. Underlying mechanisms were investigated and novel parameters defined to correlate warpage with photodefinition of ultrafine lines and vias on the board. Based on the experiments, warpage specifications for the multifunctional multilayered requirements in a proposed system-on-package (SOP) structure were defined. Experimentally validated FEM models were used to estimate the warpage during the multilayered buildup. Results show that FR-4 is not suitable for future high-density packaging needs and underscore the need for stiffer ceramic-based circuit board materials as replacement for FR-4

Evaluation of Alternative Materials for System-on-Package (SOP) Substrates

This work deals with the selection and evaluation of new board materials that can enable microminiaturized, multilayered multifunctional system-level packaging such as system-on-package (SOP) pursued by the Packaging Research Center, Georgia Institute of Technology. The effect of board properties such as coefficient of thermal expansion (CTE) and high elastic modulus upon the increase in flip chip reliability performance was investigated and guidelines for optimum board properties for realizing SOP were suggested based on the reliability results. Three different types of carbon fiber reinforced composites boards and two different kinds of inorganic boards were tested to evaluate the improvement in flip chip reliability compared to conventional glass fabric-epoxy boards (FR-4). Short carbon fiber, unidirectional carbon fiber, and carbon fiber-cloth reinforced polymer composites with a CTE close to 3 ppm//spl deg/C and three to nine times higher modulus than conventional FR-4 were selected as polymer-based composite boards. Metal matrix composites with moderate CTE ( Al/SiC; 8 ppm//spl deg/C) and ceramics with lower CTE (AlN, 4 ppm//spl deg/C) were selected as inorganic boards with high stiffness. The thermomechanical reliability of the electrical interconnections was evaluated with flip-chips assembled on five different boards by subjecting them to thermal shock treatments. Except AlN, all test vehicles fabricated with low CTE boards did not show any improvement in reliability even with underfill though they have matched CTE with Si. This is attributed to the higher dielectric stresses caused by the increased CTE mismatch between the boards and the build-up dielectric. The stress in dielectric leads to severe cyclic warpage of boards during heat cycle, resulting in dielectric fatigue cracking. With this mechanism, even underfill cannot improve the reliability. On the contrary, AlN board with highest modulus and matched CTE with Si significantly enhanced the reliability even without underfill because of its high modulus preventing cyclic warpage during thermal cycling. A new type of failure mechanism was proposed based on the optical microscopic failure mode analysis as well as analytical modeling of stress induced in the solder joints and dielectric layer. In-situ warpage of test vehicles during thermal cycling was measured in order to confirm the proposed failure mechanism. It can be concluded that to enhance the flip chip reliability without underfill, it is necessary to have high elastic modulus along with Si-matched CTE. Ultra-high stiffness is an important requirement for developing new board materials that can realize SOP concept.

The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

SOP: What Is It and Why? A New Microsystem-Integration Technology Paradigm-Moore's Law for System Integration of Miniaturized Convergent Systems of the Next Decade

In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board.

Intelligent SOP Manufacturing

Microsystems packaging is fundamentally dependent on the manufacture of microelectronic, photonic, radio frequency (RF), and MEMS devices. The system-on-package (SOP) approach has been identified as a key strategy for integrating these strategic packaging technologies. Because of rising costs, the challenge before SOP manufacturers is to offset capital investment with greater automation and technological innovation in the fabrication process. To reduce manufacturing cost, several important subtasks have emerged, including increasing fabrication yield, reducing product cycle time, maintaining consistent levels of product quality and performance, and improving the reliability of processing equipment. Because of the large number of steps involved, maintaining product quality in an SOP manufacturing facility requires the control of hundreds of process variables. The interdependent issues of high yield, high quality, and low cycle time are addressed by the ongoing development of several critical capabilities in state-of-the-art computer-integrated manufacturing (CIM) systems: in situ process monitoring, process/equipment modeling, real-time process control, and equipment diagnosis. Recently, the use of computational intelligence in various manufacturing applications has increased, and the SOP manufacturing arena is no exception to this trend. Artificial neural networks, genetic algorithms (GAs), and other techniques have emerged as powerful tools for assisting CIM systems in performing various process monitoring, modeling, and control functions. This paper reviews current research in these areas, as well as the potential for deployment of these capabilities in state-of-the-art SOP manufacturing facilities.

Electromagnetic Interference (EMI) of System-on-Package (SOP)

Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration.

Cost and Performance Tradeoff Analysis in Radio and Mixed-Signal System-on-Package Design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.

Embedded Resistors and Capacitors for Organic-Based SOP

System-on-package (SOP) architectures take advantage of compact, high-performance designs to place the maximum amount of functionality on a subsystem that can then be mounted on a lower-cost, lower density interconnect board. Embedding passive components is a key technology in achieving these goals since this enables smaller SOP substrate footprints or, equivalently, higher functional density, along with better power distribution, increased design flexibility and improved reliability. The resulting footprint areas of integrating capacitors will have more of an effect on the layer count of SOP assemblies than will integrating resistors due to the rather low specific capacitances of most embeddable dielectrics, but the situation is improving steadily. It may be necessary to use two different dielectric materials to cover the entire required range. The inherently lower parasitic inductance of embedded capacitors makes them much more useful in decoupling than surface mount capacitors, enabling more robust power distribution and decreased power/ground noise. The key to this performance enhancement in large boards is the use of a thin dielectric to decrease the inductance but, for the smaller SOP substrates, the dielectric constant must also be high to provide sufficient decoupling capacitance in the reduced area.

Thermal Modeling and Performance of High Heat Flux SOP Packages

This paper explores the thermal challenges in advanced system-on-package (SOP) electronic structures, as well as candidate thermal solutions for these highly demanding cooling needs. The heat fluxes on the active surfaces are expected to approach 100 W/cm/sup 2/. The impact of this high flux is exacerbated by the relatively low thermal conductivity of the organic materials in SOP packaging. Detailed three-dimensional (3-D) finite element simulations were used to study the temperature distributions in a typical SOP package, and to provide guidance for the development and implementation of compact thermal models. These models were used to evaluate and compare the performance of various thermal technologies and to establish the most promising thermal management alternatives. The use of direct liquid cooling, by immersion of the components in inert, nontoxic, high dielectric strength perfluorocarbon liquids was seen to provide effective cooling over a range of anticipated SOP power dissipations.

Stackable system-on-packages with integrated components

In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in the Z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.

System-Level Reliability Assessment of Mixed-Signal Convergent Microsystems

The next-generation convergent microsystems, based on system-on-package (SOP) technology, require up-front system-level design-for-reliability approaches and appropriate reliability assessment methodologies to guarantee the reliability of digital, optical, and radio frequency (RF) functions, as well as their interfaces. Systems approach to reliability requires the development of: i) physics-based reliability models for various failure mechanisms associated with digital, optical, and RF Functions, and their interfaces in the system; ii) design optimization models for the selection of suitable materials and processing conditions for reliability, as well as functionality; and iii) system-level reliability models understanding the component and functional interaction. This paper presents the reliability assessment of digital, optical, and RF functions in SOP-based microsystems. Upfront physics-based design-for-reliability models for various functional failure mechanisms are presented to evaluate various design options and material selection even before the prototypes are made. Advanced modeling methodologies and algorithms to accommodate material length scale effects due to enhanced system integration and miniaturization are presented. System-level mixed-signal reliability is discussed thorough system-level reliability metrics relating component-level failure mechanisms to system-level signal integrity, as well as statistical aspects.

Foreword Special Issue on System-On-Package (SOP)

Foreword Special Issue on System-On-Package (SOP)