System-level Design Tools Research Articles

Reduced-Order Computational-Fluid-Dynamics-Based Analysis of Aviation Heat Exchangers

The goal envisioned for the Reduced-Order Computational Fluid Dynamics and Heat Transfer (ROM-CFDHT) procedure is obtaining fast turnaround in simulation time so that computational fluid dynamics can form a component of a system-level design tool. To accomplish this, a set of finite-element schemes is proposed, including the choice of the quadratic interpolation functions, the penalty approach, an intelligent error-control capability, a continuation method, a restart procedure that restores the integrity of the error-control scheme when the procedure encounters difficulties, and the consistent flux method. It is shown that for a natural convection problem simulation using fewer than 20 elements produces Nusselt number results that agree with models using thousands of elements, with simulation time in seconds rather than hours. Forced convection over an asymmetrically laidout bank of tubes is simulated as another test of the proposed procedure. Three values of the Reynolds number, , 100, 1000 are investigated using two grids with significantly different levels of resolution and quality. The local distributions of show some differences between the grids, but the mean results are comparable. The coarse grid could not calculate the case due to poor resolution and grid quality. A combination of grid resolution and choice of schemes enables successful simulation.

High-level modeling of communication-centric applications: Extensions to a system-level design and virtual prototyping tool

High performance streaming applications require hardware platforms featuring complex, multi-level interconnects. These applications often resemble a task-farm, where many identical tasks listen to the same input channel. Usual embedded system design tools are not well adapted to capture these applications. In particular, the non-uniform memory access (NUMA) nature of the platforms induces latencies that must be carefully examined. The paper proposes a multi-level modeling methodology and tools (TTool, SoCLib) that have been extended to model the characteristics of streaming applications (multiple tasks, non deterministic behavior, I/O devices) in UML/SysML, and to automatically generate a virtual prototype that can be simulated with high precision. The paper uses a typical streaming application to show how latencies can be estimated and fed back to diagrams.

A Design Optimization Tool for Maximizing the Power Density of 3-Phase DC–AC Converters Using Silicon Carbide (SiC) Devices

The emergence of wide-bandgap devices, e.g., silicon carbide (SiC), has the potential to enable very high-density power converter design with high-switching frequency operation capability. A comprehensive design tool with a holistic design approach is critical to maximize the overall system power density, e.g, by identifying the optimal switching frequency. This paper presents a system level design tool that optimizes the power density (volume or mass) of a three-phase, two-level dc-ac converter. The design tool optimizes the selection of the devices, heatsink and passive components (including the design of the line, electromagnetic interference (EMI), and dc-link filters) to maximize the power density. The structure of the optimization algorithm has been organized to reduce the number of potential design combinations by over 99%, and thus, produces fast simulation times. The design tool predicts that when SiC devices are used instead of Si ones, the power density is increased by 159.4%. A 5 kW, 600-V dc-link, three-phase, two-level dc-ac converter was experimentally evaluated in order to confirm the accuracy of the design tool.

Optimized pure hardware FPGA-based implementation of active disturbance rejection control

The optimized pure hardware fixed-point implementation of the active disturbance rejection control algorithm on the field programmable gate array (FPGA) is presented in this paper. The optimization of the FPGA resource occupancy is provided with the simulation-based algorithm refinement, the selection of the optimal hardware structure and the modularity principle. In contrast to the conventional very high speed integrated circuit hardware description language (VHDL) approach, the implementation of the proposed optimal hardware design is realized by the system-level design tool, i.e. Xilinx’s System Generator $$^{\mathrm{TM}}$$ (XSG). Our methodology demonstrates distinct advantages such as the shorter development time and a simpler optimization procedure of the FPGA resource occupancy. Further, automatically converting the specified XSG model into the VHDL code significantly reduces the coding efforts. The experimental results largely coincide with the simulations and confirm satisfactory system performances in the different working conditions.

Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs

This article introduces a Cyber-physical Co-Simulation Framework (CPCSF) for design and analysis of smart cells that enable scalable battery pack and Battery Management System (BMS) architectures. In contrast to conventional cells in battery packs, where all cells are monitored and controlled centrally, each smart cell is equipped with its own electronics in the form of a Cell Management Unit (CMU). The CMU maintains the cell in a safe and healthy operating state, while system-level battery management functions are performed by cooperation of the smart cells via communication. Here, the smart cells collaborate in a self-organizing fashion without a central controller instance. This enables maximum scalability and modularity, significantly simplifying integration of battery packs. However, for this emerging architecture, system-level design methodologies and tools have not been investigated yet. By contrast, components are developed individually and then manually tested in a hardware development platform. Consequently, the systematic design of the hardware/software architecture of smart cells requires a cyber-physical multi-level co-simulation of the network of smart cells that has to include all the components from the software, electronic, electric, and electrochemical domains. This comprises distributed BMS algorithms running on the CMUs, the communication network, control circuitry, cell balancing hardware, and battery cell behavior. For this purpose, we introduce a CPCSF that enables rapid design and analysis of smart cell hardware/software architectures. Our framework is then applied to investigate request-driven active cell balancing strategies that make use of the decentralized system architecture. In an exhaustive analysis on a realistic 21.6kW h Electric Vehicle (EV) battery pack containing 96 smart cells in series, the CPCSF is able to simulate hundreds of balancing runs together with all system characteristics, using the proposed request-driven balancing strategies at highest accuracy within an overall time frame of several hours. Consequently, the presented CPCSF for the first time allows us to quantitatively and qualitatively analyze the behavior of smart cell architectures for real-world applications.

Belling the CAD: Toward Security-Centric Electronic System Design

In order to keep pace with the growing complexity of integrated circuits (ICs), IC and system designers are increasingly using electronic system level (ESL) design tools. ESL tool sales were around $460 million in 2011. The value of the ICs designed using these tools is at least an order of magnitude more. Concurrently, advanced IC reverse engineering techniques are being developed and used by attackers. In response, several anti-reverse engineering techniques have been proposed for integration into the IC design flow. An important class of defenses hardens the controllers that orchestrate the functionality of designs generated by ESL tools. We demonstrate an attack to recover the controller in any ESL-generated design even if the controller has been hardened using state-of-the-art controller hardening techniques. The attack analyzes the unhardened parts of the controller (i.e., the controller output logic and datapath) and reconciles this information with the architectural, controller, and timing constraints implicit in and underlying all ESL design methodologies. We then propose a countermeasure that inserts decoy connections into an ESL tool-generated design to thwart reverse engineering. We introduce a security metric to quantify the effectiveness of the developed attacks and defenses. We demonstrate the attack and defenses on designs generated by state-of-the-art ESL tools.

System‐level assertions: approach for electronic system‐level verification

As design of digital systems become more complex and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Now that design at the register transfer level (RTL) has reached its maturity, the focus is shifting to electronic system level (ESL) design tools, languages and methodologies. At the centre of this and perhaps the most challenging are verification methods and tools to use for verifying designs at the ESL. This study presents a new concept of system-level assertions for ESL verification. It also demonstrates an environment for functionally verifying system-level designs using these system-level assertions. The proposed environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilises them for system-level verification. In this environment, designs are modelled in SystemC-transaction level modelling 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog Direct Programming Interface mechanism, and designs that are described in SystemC are verified against system-level assertions in the course of SystemVerilog simulation.

A Case Study of FPGA Blokus Duo Solver by System-Level Design

This paper presents a case study to design a Blokus Duo solver by using our system-level design toolkitnamed SystemBuilder. We start with a modeling of the Blokus nDuo solver by C language and communication APIs which are provided by SystemBuilder. Then, we iteratively verified and tuned the parameters in the solver by running the model on a general computer in order to improve the performance of the solver. Finally, the implementation on FPGA was automatically generated from the model by SystemBuilder. Despite the FPGA implementation, we have never written hardware description language throughout the case study. The case study demonstrates the easiness to design system on FPGA by System-level design tools.

Perforated Plates of Inertial Sensors – Modeling by Effective Material Properties

Abstract In this paper a method for the modeling of flexible perforated plates by continuous ones is presented using the example of an accelerometer. This model order reduction (MOR) by effective material properties enables the accurate simulation of out-of- plane modes needed for drop tests e.g. based on the system level design tool MEMS+ library building blocks.

An FPGA-based approach to the automatic generation of VHDL code for industrial control systems applications: A case study of MSOGIs implementation

When used for specifying control systems, system level design tools such as Xilinx System Generator (XSG) allows the use of Simulink for designs based on Field Programmable Gate Arrays (FPGAs). This increases productivity by reducing the wide gap between control system designers and FPGA-based implementations. However, there is still a need for new methods to bridge the gap since a direct implementation from XSG may not be an optimal solution when constraints are imposed. This is particularly true for resource-dominated circuits, where the number of operational units exceed the number of available resources. This paper presents both a methodology and a tool aimed at automatically reducing the required resources, in particular in systems where the required sampling period is greater than the computation time delay. An automatic process of converting XSG specifications into efficient Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is described. The process mainly involves customized fixed-point hardware definition, Data Flow Graph (DFG) extraction, resource-constrained and latency-constrained scheduling and VHDL specification of the system, inter alia. This solution considerably improves on the results obtained by XSG.

A Fast Performance Estimation Framework for System-Level Design Space Exploration

This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.

System-Level Performance Evaluation of Very High Complexity Media Applications : A H264/AVC Encoder Case Study

Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application; a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms.

Implementation of a CNN-based retinomorphic model on a high performance reconfigurable computer

The complexity of hardware design methodologies represents a significant difficulty for non-hardware focused scientists working on accelerating the simulation of complex bio-inspired applications. An emerging generation of electronic system level (ESL) design tools is been developed, which allow software–hardware codesign and partitioning of complex algorithms from high level language (HLL) descriptions. These tools, together with high performance reconfigurable computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of highly parallelizable algorithms. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, are analyzed. A model for the first synapse of the retina, based on a discrete-time sequential CNN architecture suitable for FPGA implementation proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results showed that, with a minimum development time, a 10×acceleration, when compared to the software emulation, can be obtained.

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.

Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design

We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

Real-time application to multiprocessor-system-on-chip mapping strategy for system-level design tool

A new static mapping technique is presented that can be integrated in a system-level design tool for modelling and simulating real-time applications onto an embedded multiprocessor system. The results of preliminary experiments indicate that the proposed two-phase mapping approach can achieve a good trade-off between the efficiency in resource usage and processor load balancing, as well as the minimisation of the inter-processor communication cost.

New Mechatronics Development Techniques for FPGA-Based Control and Simulation of Electromechanical Systems

Field programmable gate arrays (FPGAs) have been widely adopted in high volume commercial applications, but not as much in the industrial control and simulation arenas. Due to the attractive features of FPGAs, such as their inherent flexibility, performance, parallelism, and low-level reconfigurability, industrial control design and simulation vendors have been creating the next generation FPGA development tool chains that are designed for engineers with little or no digital design expertise. The goal of these next generation system-level design tools is to empower control design, simulation, and signal processing engineers to harness the full power of the FPGA technology, while providing relatively competitive performance and resource usage, as compared to traditional text-based hardware description level (HDL) methods. This paper discusses some of the traditional challenges that prohibited wide adoption of FPGAs in the industrial control and simulation fields, and how new graphical system design tools are helping mechatronics engineers leverage the full power of FPGAs as deployment platforms. Moreover, it discusses some particularly useful development techniques for FPGA-based control and simulation in mechatronics applications.

Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling

This paper presents a new technique, called Adaptive Stochastic Gradient Voltage-and-Task Scheduling (ASG-VTS), for power optimization of multicore hard realtime systems. ASG-VTS combines stochastic and energy-gradient techniques to simultaneously solve the slack distribution and task reordering problem. It produces very efficient results with few mode transitions. Our experiments show that ASG-VTS reduces number of mode transitions by 4.8 times compared to traditional energy-gradient-based approaches. Also, our heuristic algorithm can quickly find a solution that is as good as the optimal for a real-life GSM encoder/decoder benchmark. The runtime of ASG-VTS is 150 times and 1034 times faster than energy-gradient based and optimal ILP algorithms, respectively. Since the runtime of ASG-VTS is very low, it is ideal for design space exploration in system-level design tools. We have also developed a web-based interface for ASG-VTS algorithm.

Experiment on a system-level design tool

System-level design pertains to questions of product or system architecture, configuration, and layout; and as such, provides an important bridge between conceptual engineering design work and detailed design decisions. Prior research indicates that this phase of design is important to successful outcomes of design processes, yet it is not well understood. This paper reports the development and experimental testing of a system-level design tool that aids student designers in improving design quality through enhanced understanding of system-level design issues and alternative selection. We found that use of the tool produced significant improvements in design quality among two experimental groups of mechanical engineering students. By developing and testing this tool, we hope to prove the usefulness of tools that aid engineering design at a system level, particularly in reducing heavily iterative and non-productive tasks.

Towards a configurable SoC MPEG-4 advanced simple profile decoder

The evaluation of various architectural designs to allow low bandwidth digital video decoding and reception over the digital audio broadcasting network, and the problem of how to find and implement an optimal HW/SW partition on a Programmable Logic Device with an embedded ARM9 processor are focused. Profiling and design space exploration techniques are applied to the advanced simple profile of an MPEG-4 decoder, for which an innovative SystemC-based system-level design tool, called CASSE, has been used. Simulations results showed that a throughput of 15 QCIF frames per second can be achieved with a low area and low power implementation. Details of this implementation and where the results differ from simulation are presented.