Abstract
Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application; a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms.
Highlights
The architectural complexity of System-on-Chip (SoC)based embedded systems, as well as the design re- quirements regarding real-time performance, high flexibility, low power consumption and cost greatly complicate the system design
Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages
We demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient performance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems
Summary
The architectural complexity of System-on-Chip (SoC)based embedded systems, as well as the design re- quirements regarding real-time performance, high flexibility, low power consumption and cost greatly complicate the system design. In order to resolve the increasing design complexity, researchers have recently come up with a new design concept called system-level design [1] For this purpose, a new generation of system-level tools and methodologies has been introduced to efficiently explore the design space of heterogeneous signal processing systems. The Y-chart layer’s based approach, considered as the most popular approach for designing multimedia oriented systems, is already being followed in most recent system-level design works [1] It tries to improve the shortcomings of the classical HW/SW co-design approach by abandoning the usage of low-level (instructionlevel or cycle-accurate) simulators for the design space exploration at an early stage of the flow, and abandoning a single system specification to describe both hardware and software parts. The architecture model defines the architecture resources, captures their timing characteristics, and simulates the performance consequences of the application events
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