Optimized pure hardware FPGA-based implementation of active disturbance rejection control

Abstract

The optimized pure hardware fixed-point implementation of the active disturbance rejection control algorithm on the field programmable gate array (FPGA) is presented in this paper. The optimization of the FPGA resource occupancy is provided with the simulation-based algorithm refinement, the selection of the optimal hardware structure and the modularity principle. In contrast to the conventional very high speed integrated circuit hardware description language (VHDL) approach, the implementation of the proposed optimal hardware design is realized by the system-level design tool, i.e. Xilinx’s System Generator $$^{\mathrm{TM}}$$ (XSG). Our methodology demonstrates distinct advantages such as the shorter development time and a simpler optimization procedure of the FPGA resource occupancy. Further, automatically converting the specified XSG model into the VHDL code significantly reduces the coding efforts. The experimental results largely coincide with the simulations and confirm satisfactory system performances in the different working conditions.