System-level Design Space Exploration Research Articles

System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints

System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints

Embedded Systems Design Space Exploration Under Security Constraints

Design space exploration (DSE) is a key activity in any embedded system design flow. With the remarkable increasing in the connectivity to the internet, embedded systems are becoming the target of different cyber-attacks. As security emerges as a major design concern, DSE should be aware of the security aspect at a higher level of abstraction. On the other hand and to our best knowledge, there is no a comprehensive survey on this topic, hence the need to establish a comprehensive survey for existing security-aware DSE approaches for embedded systems at the system level. To meet this objective, we first selected and summarized twenty-two pertinent works. They were analyzed based on a set of criteria. The outcomes of this survey are a set of recommendations that can help embedded systems designers to better dealing with security at system-level DSE stage. The presented survey ends by proposing some potential promising future trends that can be investigated by researchers to pursue the research in related topics.

Early Area and Power Estimation Model for Rapid System Level Design and Design Space Exploration

Power and area estimation in the early stage of designing is very critical for a system. This paper presents the neural network-based early area and power estimation model. The flow starts with the training of the neural network model from the selected behavioral level parameters, which imposes to provide accurate estimations. The model accuracy is validated against ITC99 benchmark programs. The run-times are faster than the synthesis run-times. For the ASIC-based designs, the proposed model took 5 seconds, while Synopsys Design Compiler took 5 minutes. In terms of timing, the estimation speed is more than the order of magnitude faster than the conventional synthesis-based approach. The modeling methodology provides a better, accurate, and fast area and power estimations, at an early stage of the Very-Large-Scale Integration (VLSI) design. In addition, the model eliminates the need for synthesis-based exploration and provides the design picking before synthesis.

System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System

Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module– (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Machine learning (ML) accelerators have a broad spectrum of use cases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on processing element (PE) array dimensions and SRAM buffer sizes. The 3-D integration packs more compute or memory in the same 2-D footprint, which can be utilized to build more powerful or energy-efficient accelerators. However, 3-D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3-D systolic accelerators. Using this framework, different 3-D-partitioned accelerator configurations are proposed and evaluated. The 3-D-stacked accelerator designs are modeled using the hybrid wafer bonding technique with a 1.44- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pitch of 3-D connection. Results show that different partitioning of the systolic array and SRAM buffers in a four-tier 3-D configuration can lead to either 1.1– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.9\times $ </tex-math></inline-formula> latency reduction or 1– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> energy reduction compared to the baseline design of the same 2-D area footprint. It is also shown that by carefully organizing the systolic array and SRAM tiers using logic over memory, the temperature rise with 3-D across benchmarks can be limited to 6 °C.

SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems

This work faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototype SystemC-based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper.

Sustainability-Oriented Evaluation and Optimization for MPSoC Task Allocation and Scheduling under Thermal and Energy Variations

Aiming at high performance, more and more Cyber-Physical Systems (CPSs) adopt Multiprocessor System-on-Chips (MPSoCs) as computation units. However, due to increasing integration of transistors on a die, the power densities together with performance variations of MPSoC chips have been increasing dramatically. Consequently, the MPSoC-based CPSs might become unsustainable and unreliable. Although various Task Allocation and Scheduling (TAS) heuristics have been proposed to minimize the hotspot time (i.e., duration of thermal emergency) and energy consumption of MPSoC designs, few of them can guarantee the highest performance yield under process variations without violating energy, thermal and timing constraints. To address these challenges, this paper proposes a novel energy- and thermal-aware TAS evaluation and optimization framework. Based on statistical model checking techniques, our approach enables accurate modeling and reasoning of the performance yield of real-time MPSoC designs under joint energy and thermal constraints. To enable system-level design space exploration, we propose a regression analysis-based method that can drastically reduce the overall exploration efforts. Experimental results show that our fully-automated approach can not only allow accurate sustainability-oriented reasoning of TAS solutions under specified thermal and energy constraints, but also enable the quick search of optimal TAS solutions on different MPSoC architectures with the highest performance yield.

Modular Active Charge Balancing for Scalable Battery Packs

High-voltage battery packs consist of series-connected lithium-ion cells and require sophisticated battery management systems (BMSs) to maintain safe operating conditions. Active cell balancing is an important task of a BMS, performed in order to improve the usable capacity of the battery pack by equalizing the charge levels of individual cells. With the emerging trend of distributed BMS topologies, the associated balancing architectures are required to be modular, consisting of homogeneous units that minimize integration efforts. In this paper, we propose a modular active charge balancing architecture along with its control scheme for implementation toward such distributed BMSs. Compared with existing approaches, our proposed architecture provides increased charge transfer capabilities, with reduced hardware and control complexity. We propose a closed-form analytical model of the balancing architecture, which can be used to perform fast system-level simulation studies and design space exploration for analyzing efficient device combinations. A hardware implementation of the proposed balancing architecture is developed and measurements made with it are used to validate each part of our analytical model. Using the validated analytical model, we performed a case study, which shows that our proposed architecture provides a 14.5 % improvement in charge transfer efficiency compared with existing approaches.

A system-level infrastructure for multidimensional MP-SoC design space co-exploration

In this article, we present a flexible and extensible system-level MP-SoC design space exploration (DSE) infrastructure, called NASA. This highly modular framework uses well-defined interfaces to easily integrate different system-level simulation tools as well as different combinations of search strategies in a simple plug-and-play fashion. Moreover, NASA deploys a so-called dimension-oriented DSE approach, allowing designers to configure the appropriate number of, well-tuned and possibly different, search algorithms to simultaneously co-explore the various design space dimensions. As a result, NASA provides a flexible and re-usable framework for the systematic exploration of the multidimensional MP-SoC design space, starting from a set of relatively simple user specifications. To demonstrate the capabilities of the NASA framework and to illustrate its distinct aspects, we also present several DSE experiments in which, for example, we compare NASA configurations using a single search algorithm for all design space dimensions to configurations using a separate search algorithm per dimension. These proof-of-concept experiments indicate that the latter multidimensional co-exploration can find better design points and evaluates a higher diversity of design alternatives as compared to the more traditional approach of using a single search algorithm for all dimensions.

HW/SW co‐design of dedicated heterogeneous parallel systems: an extended design space exploration approach

This work faces the problem of the hardware/software (HW/SW) co-design of dedicated electronic digital systems based on heterogeneous parallel architectures. In particular, other than describing the reference HW/SW co-design flow, it proposes an extension of a previous system-level design space exploration approach able to suggest to the designer an HW/SW partitioning of the system functionalities specification and a mapping of the partitioned entities onto an automatically defined ‘heterogeneous multi multi-core processor’ architecture.

Fitness Prediction Techniques for Scenario-Based Design Space Exploration

Modern embedded systems are becoming increasingly multifunctional. The dynamism in multifunctional embedded systems manifests itself with more dynamic applications and the presence of multiple applications executing on a single embedded system. This dynamism in the application workload must be taken into account during the early system-level design space exploration (DSE) of multiprocessor system-on-a-chip (MPSoC)-based embedded systems. Scenario-based DSE utilizes the concept of application scenarios to search for optimal mappings of a multi-application workload onto an MPSoC. The scenario-based DSE uses a multi-objective genetic algorithm (GA) to identifying the mapping with the best average quality for all the application scenarios in the workload. In order to keep the exploration of the scenario-based DSE efficient, fitness prediction is used to obtain the quality of a mapping. This fitness prediction is performed using a representative subset of application scenarios that is obtained using co-exploration of the scenario subset space. In this paper, multiple fitness prediction techniques are presented: stochastic, deterministic, and a hybrid combination. Results show that, for our test cases, accurate fitness prediction is already provided for subsets containing only 1-4% of the application scenarios. Larger subsets will obtain a similar accuracy, but the DSE will require more time to identify promising mappings that meet the requirements of multifunctional embedded systems.

Exploiting domain knowledge in system-level MPSoC design space exploration

System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded multimedia systems. During system-level DSE, system parameters like, e.g., the number and type of processors, and the mapping of application tasks to architectural resources, are considered. The number of design instances that need to be evaluated during such DSE to find good design candidates is large, making the DSE process time consuming. Therefore, pruning techniques are needed to optimize the DSE process, allowing the DSE search algorithms to either find the design candidates quicker or to spend the same amount of time to evaluate more design points and thus improve the chance of finding even better candidates. In this article, we study several novel approaches that exploit domain knowledge to optimize the DSE search process. To this end, we focus on DSE techniques based on genetic algorithms (GA) and introduce two new extensions to a GA to optimize its search behavior. Experimental results demonstrate that the extended GAs perform at least as well, but typically significantly better than a reference (non-optimized) GA.

System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation

For sensor nodes deployed at small distances, computation energy along with radio energy determines the battery life. We have proposed a system-level design space exploration methodology in [1] for searching an energy-efficient error-correcting code (ECC). This methodology takes into account the computation and the radio energy in an integrated manner. In this paper, we validate this methodology by deploying the Imote2 nodes and measuring energy values under different operating modes, e.g., with and without ECC. In this process, we propose a validation framework and node energy model. Experimental results validate the methodology and show that with ECC we can save up to 14% transmitter energy under a certain set of conditions. The main contribution of this paper is that it establishes experimentally that our methodology is effective in exploration of various node configurations and finding an energy-efficient solution.

VMODEX: A novel visualization tool for rapid analysis of heuristic-based multi-objective design space exploration of heterogeneous MPSoC architectures

System-level computer architecture simulations create large volumes of simulation data to explore alternative architectural solutions. Interpreting and drawing conclusions from this amount of simulation results can be extremely cumbersome. In other domains that also struggle with interpreting large volumes of data, such as scientific computing, data visualization is an invaluable tool. Such visualization is often domain specific and has not become widely studied and utilized for evaluating the results of computer architecture simulations. In this paper, we introduce our novel interactive visualization tool, called VMODEX, which is developed to support system-level design space exploration of MPSoC architectures. In our tool, the design space is modeled as a tree in which both the design parameters and criteria are shown in a single view. VMODEX is able to handle large design spaces and allows designers to look at the data from different perspectives and at multiple levels of abstraction. Due to the exponential design space in real problems and multiple criteria to be considered, heuristic searching algorithms are often used to trim down a large design space into a finite set of points and provide the designer a set of tradable solutions with respect to the design criteria. In VMODEX, besides the techniques provided for visualizing the DSE results, additional capabilities are developed to understand the dynamic search behavior of heuristic searching algorithms.

A High-Level Power Model for MPSoC on FPGA

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the technique highly useful in the context of early system-level design space exploration. We have integrated the power estimation technique in a system-level MPSoC synthesis framework. Using this framework, we have designed a range of different candidate MPSoC architectures and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively. key words: design space exploration, system-on-a-chip (SoC), SystemC, UML, 3D graphics

A High-level Microprocessor Power Modeling Technique Based on Event Signatures

This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called `event signatures', operates at a higher level of abstraction than commonly-used instruction-set simulator (ISS) based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. In this paper, we also compare our power estimation results to those from the instruction-level simulators Wattch and Sim-Panalyzer. In these experiments, we demonstrate that with a good underlying power model, the signature-based power modeling technique can yield accurate estimations (a mean error of 3.1% compared to Wattch in our experiments). At the same time, our signature-based power modeling technique is at least an order of magnitude faster than the simulations performed by Wattch or Sim-Panalyzer.

Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)

Reconfigurable devices in large complex systems allow the reduction of the amount of required resources. They serve as run-time re-usable devices for performance critical data-oriented processes. However, the use of reconfigurable devices within large systems greatly increases the design complexity. The designer´s task gets even harder when the goal is a resource efficient solution. Constructing a good design requires the consideration of many design alternatives. With today´s complex systems and the resulting degrees of freedom the designer should be assisted by sophisticated design space exploration tools. However, all known system-level design space exploration tools do not exploit the potentials dynamic hardware reconfiguration exposes. Moreover, the implementation of selected solutions poses an additional challenge and also requires a cycle-level simulation. This paper presents a novel design methodology which is able to overcome these drawbacks by integrating state-of-the-art temporal partitioning approaches for dynamic hardware reconfiguration into system-level design space exploration.

MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution

Fully integrated system level design space exploration methodologies are essential to guarantee efficiency of future large scale system on programmable chip. Each design step in the design flow from system architecture to place and route represents an optimization problem. So far, different tools (computer architecture, design automation) are used to address each problem separately with at best estimation techniques from one level to another. This approach ignores the various and very diverse vertical relations between distinct levels parameters and provides at best local optimization solutions at each step. Due to the large scale of SoC, system level design methodologies need to tackle the system design process as a global optimization problem by fully integrating physical design in the design space exploration. We propose MOCDEX, a multiobjective design space exploration methodology, for multiprocessor on chip which closes the gap between these associated tools in a fully integrated approach and with hardware in the loop. A case study of a 4-way multiprocessor demonstrates the validity of our approach.

Low-power system-level design of VLSI packet switching fabrics

System-level design of packet switching fabrics focuses on performance metrics and rarely considers the physical requirements that are usually addressed later at the circuit-level. However, low-power dissipation has become a major requirement in such fabrics dictated by the requirements of emerging applications and by the recent advances in fabrication and VLSI technologies. This paper proposes a framework for system-level design of packet switching fabrics that integrates performance specifications along with physical requirements and constraints. Moreover, realistic traffic models are used to derive the transition activity and the packet arrival and departure events needed for power estimation. Physical requirements are defined by an architectural model for power dissipation based on the stochastic traffic model, models for silicon area, chip count, and input-output pins, which provide a complete system-level specification of the fabric. Performance constraints are also derived from the stochastic traffic model. This framework formulates and solves the power optimization problem subject to those physical and performance constraints as an integer nonlinear optimization problem. The results obtained emphasize the importance of traffic-driven system-level optimization and show the efficiency of this framework as a system-level design space exploration tool.