System In Package Module Research Articles

Conductive water-based graphene suspension for electromagnetic interference shielding via spray coating on SiP module

Conductive inks have been widely used to develop electronic devices, such as sensors, RFID antennas, and transistors. Electronic utilization is a coating that forms conductive films for electromagnetic interference shielding (EMI Shielding). This process also can be employed to cover electronic modules called System in Package (SiP). A technology known as conformal shielding utilizes spray coating with metallic inks to form a conductive layer over the SiP. Traditionally, copper or silver inks have been the primary materials employed due to their high electrical conductivity. Conversely, these metallic inks are associated with significant costs, environmental impacts, and complex production methods. In this context, water-based graphene dispersion could be an alternative to EMI Shielding for electronic chips. Graphene is attractive due to its excellent electrical and thermal properties, reduced cost, and being an environmentally friendly material. In this study, a water-based graphene suspension was developed and applied via spray coating to form films for electromagnetic shielding. The graphene dispersion in water utilized Carboxymethyl cellulose (CMC). Characterizations of the graphene suspension, including morphology, particle size distribution, and chemical analysis, were conducted. The resistivity of the resulting films and their shielding effectiveness (SE) were measured. Electronic chip modules were painted to assess coverage. The study demonstrated the successful formulation of a stable water-graphene suspension exhibiting favorable electrical resistivity (2.8 × 10−2 Ω.cm) after drying at 300 °C for 1 h. The resulting film achieved a shielding effectiveness of −9 dB at 1.0 GHz. Graphene film completely covered the electronic chips, indicating an alternative conformal shielding.

Ultra-Thin SSPP-Based Sheet for Suppressing Microwave Radiated Emission in SiP Modules

System-in-Package (SiP) has been facing the problem of excessive radiation leakage. In this article, a novel technique of absorptive sheet is proposed for suppressing unwanted microwave radiated emission in an advanced high-speed SiP module backed with a heat sink. Different from the conventional periodic resonant structure or absorptive film, the electromagnetic energy is consumed based on the mechanism of spoof surface plasmon polaritons (SSPP) in our design. By adjusting the length of the metallic strip to control its k-dispersion characteristics, the SSPP modes could be excited around one frequency point. Therefore, a relatively wide absorption band is created by arranging stepped strips in arrays on a dielectric medium. According to the electromagnetic distribution in the SiP module, SSPP-based absorptive units are circularly arranged to constitute the complete proposed absorptive sheet with adequate absorption efficiency. From the simulated results, the proposed design can provide 90 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> absorption performance covering a wide frequency range of 26.3–31.6 GHz, with a substrate thickness of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\lambda _{L}$</tex-math></inline-formula> /228 and a total thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\lambda _{L}$</tex-math></inline-formula> /134, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\lambda _{L}$</tex-math></inline-formula> is the wavelength at the lowest operating frequency. Finally, the proposed absorptive sheet is fabricated and measured, where measurement results agree well with the simulated ones, which corroborates the feasibility and effectiveness of applying the SSPP-based absorbing techniques for suppressing the radiated emission in microwave and millimeter-wave frequency range in SiP modules.

Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in- Package (SiP) Modules

System-in-package (SiP) modules are widely used in portable electronics such as Internet of Things (IoT) devices and mobile consumer equipment since they integrate multiple components in a single package and thus facilitate device miniaturization. An advanced packaging technology referred to as dual-side molding (DSM) has recently been proposed as a means of achieving even smaller form factors and lower cost solutions. However, shrinking the package size reduces the solder joint connection area between the SiP module and the printed circuit board (PCB). Consequently, the board-level drop reliability may be severely impaired. Accordingly, the present study utilizes a numerical model to investigate the board-level solder joint reliability of a DSM SiP package in drop impact tests performed in accordance with the Joint Electron Device Engineering Council (JEDEC) standard. The validity of the numerical model combined with a full-factorial design method is then employed to examine the effects of the main design parameters of the DSM SiP package on the reliability of the solder joints in the drop impact test. Overall, the present results show that a higher EMC coverage of the solder ball joints yields a significant improvement in the solder joint reliability. In addition, a larger solder joint volume is beneficial in reducing the solder joint stress by absorbing a greater proportion of the impact load and energy produced in the drop impact event.

Electrothermal Analysis of System in Package for Aerospace Application

Abstract Aiming at the failure problem of aerospace electronic product at the complex space environment, the electrothermal coupling method has been used to analyze the reliability of the ten channels independently adjustable voltage conversion system in package (SIP) module based on integrated forming package, which has supplied the voltage to the remote sensing camera detector. First, the electromagnetic model and thermal model have been made based on the SIP module; second, the electrothermal coupling simulation of three working conditions at normal environment have been made, and the maximum temperature of the SIP has been calculated; then, the maximum temperature of the SIP has been also calculated at vacuum and 45 °C to analyze the performance of this SIP in the space environment; at last, some test have been made of the SIP product. Compared with the measured results, the electrothermal coupling method has much more accurate than traditional thermal method. At normal environment, the simulated temperature relative error is 2.8%. At vacuum and 45 °C environment, the simulated temperature relative error is 9%. This method ensured the performance and accuracy of the design of the SIP, which has verified the reliability of aerospace SIP module at early stage.

Research On Thermal Management Technology of System- Level Electronic Integrated Package

With the rapid development of modern electronic products, electronic products present a development trend of increasing packaging density, miniaturization and diversification of the environment. System-in-package (SiP) with the advantages of large-scale, multi-chip, and 3D three-dimensional packaging has attracted more and more attention. Due to the high-density interconnection between the components of the system-in-package circuit, the power density of the package is greatly increased, which will inevitably lead to an increase in the heat generation rate, so the research on its heat dissipation characteristics is particularly important. Introduced the theories and concepts of thermal management and heat transfer, expounded the general method of chip thermal management, took the plastic package SiP module as the research object, introduced the device-level junction-case thermal resistance and board-level junction-board thermal resistance analysis methods, introduction The heat dissipation technology of thermal conductive glue. It provides a reference for SIP package heat dissipation technology.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, II...

A Systematic Approach to the Reliability Characterization of System in Package (SiP)

Abstract System-in-Package (SiP) solutions are gaining popularity across multiple market segments, dually reducing product design complexity for Original Equipment Manufacturers (OEMs) while increasing system performance and functionality. For SiP customers, product design complexity is reduced with the integration of electrical sub-system functionality into a module that can be designed into a product with relative ease. Further, logistical complexity is reduced, with the supplier carrying responsibility for the sub-system's quality and reliability. In addition, OEMs benefit from the performance, functionality and form factor improvements enabled by advanced SiP packaging and substrate technologies. With the increased responsibility of SiP solutions in mind, the authors addressed a systematic approach and methodology to understand the complexity of thermo-mechanical risk and challenges in SiP solutions. A modeling and characterization methodology was used to systematically identify and mitigate reliability risks for system-in-package SiP modules. Specifically, a combination of Shadow-Moire technique, digital image correlation (DIC), reliability testing and finite element (FE) models were used to demonstrate this upstream thermo-mechanical evaluation for SiP Solutions. Empirical warpage trends for the SiP module and solder joint fatigue failure trends were in close agreement with the model output based upon design and material factor inputs to the FE models.

Notice of Retraction: Analysis of Near-Field Shielding Effectiveness for the SiP Module

In this letter, near-field scanning technology is utilized to analyze the shielding effectiveness (SE) of the system-in-package (SiP) module at the frequency of 1–6 GHz. Different definitions of the near-field SE are explored and analyzed. The SE is defined by using values of the radiated magnetic near-field from the SiP module, including the maximum value, the spatial averaged value, and the value at the same observation point, respectively. The SE defined by the spatial averaged value is a reasonable method to represent the overall SE of a well-shielded SiP module especially at low frequencies. Besides, a comparison of the SE between the reverberation chamber measurement and averaged magnetic near field is carried on. Good consistency is obtained, which confirms the reliability and efficiency of the near-field scanning method.

Technology Review of System in Package

The Moore's law is approaching to an end at today's 14 nm technology and System in Package (SiP) is a promising solution for achieving denser electronics like mobile phones with small form factors. System in package is bringing together multiple ICs of various functionality stacked in 3D fashion. A fully functional system consisting of passive elements like resistor, capacitor, inductors, electromechanical elements, antenna, and ICs like sensors, can be integrated into a single package. To meet the requirements of the end product, system design characterization becomes very important for overall success in the development of system in package. Failure analysis and testing of the end product helps improve the product yield which is a point of concern for industries while designing system in package. But system in package has proven to be a viable solution for reduction in total cost and minimize time-to-market. Hence, system in package will continue to thrive and grow into mainstream technology despite of challenges faced during the development and production phase. In this paper, summary of system in package is presented with the perspective of reviewing the research carried out to overcome the challenges, cost issues, compatibility of different functional dice, quality and reliability issues. This paper discusses the recent technological development of system in package modules and the limitations faced at various system levels while bringing multiple chips together to achieve fully functional package. This paper focuses on bridging the gap between the system integration by reviewing the research progress in the 3D IC and packaging using system in package. Some of the applications like portable electronics, automotive and wearable electronics, where the significance of system in package is more relevant are reviewed in this paper. The core challenges like thermal management, flip chip or wire bond interconnect that arise due to integration of different components and packages like package on package, package in package in the system in package are also discussed.

3D SiP Assembly and Reliability for Glass Substrate with Through Vias

Abstract Applications of Glass substrate for high performance system-in-package (SiP) products have gradually become a promising technology in recent years. Research and development activities are reported in many journal papers and conferences [1,2]. Consortiums and Alliances are also formed to gather worldwide efforts for developing glass technology. In the past, we have published our development efforts on the process of producing glass substrate with through via and build-up redistribution circuit layers (RDLs) [3]. N. Koizumi [4] first reported glass reliability issues in 2013; and the phenomena he called SE-WA-RE has caused a great concern of using glass as a substrate. Model simulations have indicated that the glass crack is related to the stress buildup by the materials and structure. In this study, we selected a dielectric material/structure set that is designed to be less stressful to the glass substrate. A better reliability result can be expected. In this paper, we will discuss an assembly structure of SiP module using the glass substrate with through-glass via (TGV) where the diameter of TGV is 100μm with thickness at 200μm. The copper plating technique to form the through via conductor is called direct-metal-on-glass (DMoG) which deposits titanium and copper directly on glass both in the wall of through vias and on glass surfaces of both sides. The first RDL is formed on both surfaces of glass substrate by semi-additive plating (SAP); then followed by build-up RDLs on top of the DMoG RDLs on both sides of the substrate also by SAP with interconnect vias to form connections between DMoG RDLs and build-up RDLs. Finally, solder mask is applied on both sides of the glass substrate leaving pad openings (SRO) for surface finish, die mounting and printed-circuit board connection purposes. At die mounting side, the SRO is 60μm in diameter with minimum pitch at 150μm. The TGV conductors connect the DMoG RDLs on both sides of the substrate. A mechanical test die with 18μm bump diameter is mounted on the build-up RDL at the substrate top side with daisy-chain design both in the test die and TGV substrate RDLs. Thus, the daisy-chain connection can go from the build-up RDL of the substrate back side to the test die on the top side of the substrate. 200 thermal-cycling test (TCT) has been performed and the daisy-chain resistances are measured before and after the 200 TCTs. It is found that 96% of daisy-chains have less than 10% of resistance change after 200 TCTs.

LTCC-based monolithic system-in-package (SiP) module for millimeter-wave applications

A miniature LTCC system-in-package (SiP) module has been presented for millimeter-wave applications. A typical heterodyne 61 GHz transmitter (Tx) has been designed and fabricated in a type of the SiP module as small as 36 × 12 × 0.9 mm3. Five active chips including a mixer, driver amplifier, power amplifier, and two frequency multipliers were mounted on the single LTCC package substrate, in which all passive circuits such as a stripline (SL) BPF, 2 × 2 array patch antenna, surface-mount technology (SMT) pads, and intermediate frequency (IF) feeding lines have been monolithically embedded by using vertical and planar transitions. The embedded SL BPF shows the center frequency of 60.8 GHz, BW of 4.1%, and insertion loss of 3.74 dB. The gain and 3-dB beam width of the fabricated 2 × 2 array patch antenna are 7 dBi and 36 degrees, respectively. The assembled LTCC 61 GHz Tx SiP module achieves an output power of 10.2 dBm and an up-conversion gain of 7.3 dB. Because of the integrated BPF, an isolation level between a local oscillation (LO) and RF signal is below 26.4 dBc and the spurious level is suppressed by lower than 22.4 dBc. By using a 61 GHz receiver (Rx) consisting of off-the-shelf modules, wireless communication test was demonstrated by comparing measured IF spectrums at the Tx and Rx part.

SiP Technology for Wireless Module Miniaturization

SiP (System in package) module provide a integrate functions, smaller and thinner package solution on electronic portable devices. For the wireless application, the advanced AoP (Antenna on package) and compartment shielding has been proposed and developed by Advanced Semiconductor Engineering (ASE), Inc. to be the next request for complex application and miniaturization solution. For AoP package, more focus on near field/wireless connection to have specific metal antenna design and attached on package surface to achieve SiP module miniaturization and perform required antenna efficiency on low frequency application. Advanced compartment shielding provide the simple method on function isolation area to prevent the electromagnetic noise interference (EMI) and high level of total radiated EMI from system product due to more complex package performance. The major benefit of novel AoP package is transfer the antenna designed on PCB to directly attached on package to reduce the PCB X/Y dimension but still keep antenna efficiency performance. The fabrication of AoP consists of following factors: 1) special substrate design to have antenna connection pads; 2) specific 3D metal frame design for antenna; 3) antenna frame attachment and over mold for package. Following these processes, AoP provide a simple process on package assembly and smaller dimension of package. For compartment shielding development in ASE, previously we design a metal can on module package to reduce EMI but induce a thickness increase. The novel compartment shielding more focus on shielding frame design inside the package to achieve simple process flow and good shielding performance, their fabrication consists the following factors: 1) specific tooth-type frame design to have shielding function for different zone in package and provide suitable slot width/pitch ratio for mold flow; 2) adhesion material for metal frame attached on substrate ; 3) over mold and laser trenching; 4) conductive material sputtering on package surface. This novel compartment shielding solution provides a simplified shielding and more reliable process on SiP module package. Wireless module was designed RF/power/Switch/Bluetooth function inside the package, the high density of electrical function is usually designed in the portable devices with small/thinner size. Advanced AoP or compartment shielding technology provides more competitive solution on SiP module miniaturization. In the paper, we will present the design for AoP and compartment shielding, process characterization and measurement of antenna and shielding performance of module to present the advantage of SiP modules with this technology application.

PMV (Plating Mold Via) interconnection development in molded SiP modules

Recently, there are increasing demands of a size reduction and a fine interconnection technology, especially for System-in-Package (SiP) module and Package on Package (POP) module in a smart phone and a wearable electronic device. In this study, we presented the Plating Mold Via (PMV) interconnection technology as an innovative fine pitch interconnection solution between substrate I/O pads and package I/O pads in molded System-in-Package (SiP) modules. Similar to the Through Mold Via (TMV), the laser mold via process is first performed to produce a through-via in the Epoxy Mold Compound (EMC) mold, but plating and Soldering process are used simultaneously to produce the metallurgical interconnection to embody the I/O pins of the over-molded surface. After the PMV technology is described, a study of PMV in the molded packaging module is followed. The study is conducted using a test vehicle of SiP module that contains flip chips, Quad Flat Non-leaded (QFN) packages and passives. It is focused on several interface reliability issues, including the interfacial strength of PMV to substrate metal pad as well as to the laser projected area of EMC, and the study of IMC at the plating metal and solder interfaces. The study clearly shows that the PMV technology is a promising fine pitch interconnect solution for various SiP modules.

Board-Folding Method for Fabrication of 3-D System in Package Devices

This paper presents a new method, based on slotting and folding of rigid printed circuit board (PCB), for creation of 3-D cuboid system in package (SIP) devices. The method, which can create folds at any angle and uses standard manufacturing and design processes and commercial off-the-shelf components, is suitable for making SIPs down to at least 1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> in volume. It offers significant advantages over current approaches to 3-D SIP fabrication, particularly in terms of simplified manufacturing and increased packing density, as it eliminates the need for connectors or flex tapes to form folds. The method involves removing substrate material, using a dicing saw to cut a slot at the area where the fold is to be formed, and then applying heat to the area and forming the fold. Once cooled the fold remains rigid and the electrical tracks remain intact. The optimum parameters for creating a 90° fold in a PCB using this method were identified in a designed experiment with variables including substrate material, temperature, cut depth, and conductor width. Having identified the optimum process parameters, 25-mm × 10-mm × 10-mm × 10-mm cuboid test modules were fabricated and reliability screening involving temperature storage, temperature cycling, temperature-humidity, and shock/vibration was carried out. All of the modules passed reliability screening test. Finally, a functional system-in-cube module was fabricated using the folding method. The module, which combines environmental stress sensors and a microcontroller in a 1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> package, was intended for deployment as a prognostic reliability monitor. The monitor was evaluated over a range of temperature and humidity and underwent shock/vibration testing without failure. This is believed to be the first time that a board-folding approach has been used to fabricate 3-D SIP modules.

Novel ultra-compact quad-band System-in-Package (SiP) module with IC embedded in substrate based on SESUB technology.

This paper presents a novel ultra-compact System-in-Package (SiP) module with highly integrated wireless connectivity devices combining a set of 4 standards: WLAN, Bluetooth, FM and GPS. Besides an IC, the SiP module consists of RF filters, SMD components and a Single-Chip RF Front-end. The main IC is embedded inside the substrate and basics of SESUB technology are described. For electromagnetic compatibility and physical protection a metal EMI shield has been used. The total size of solution presented is 8.0×7.5×1.3mm3 demonstrating significant miniaturization over current module technology. The embedding process and SiP module routing has shown benefits in electrical and mechanical performance.

MUF Technology Development for SiP Module

In this study, we developed the molded underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on minimizing voids between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding compound (EMC) selection approach, air vent design of cavity vacuum molding, and results of void free from Design of Experiment (DOE) of several SiP module layouts. In the end, Scanning Acoustic Tomography (SAT) result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.

Fully integrated UHF RFID mobile reader with power amplifiers using System-in-Package (SiP)

A fully integrated system-in-package (SiP) for UHF (860-960MHz) RFID mobile reader is presented. The SiP is made up of an UHF transceiver, a power amplifier (PA), and two baluns. The UHF transceiver was designed in TSMC 0.18µm Si CMOS and the PA was developed with InGaP/GaAs hetero-junction-bipolar transistor (HBT) technology. The transceiver IC is fully integrated for mobile UHF RFID applications and the PA has high efficiency and linearity with 24dBm output power for wireless RFID communications over a distance of 1m. The total size of the SiP module is 11mm × 11mm. The measured data show a transmitter gain of 19.2dB, total current of 253mA and adjacent channel power ratio (ACPR) of -41.8dBc with the second harmonic performance of -57.6dBc. Also, TX-RX leakage was reduced by careful power amplifier and board designs in small SIP module implementation.

Molded Underfill (MUF) Technology Development for SiP Module with Fine Flip Chip

In this study, we developed the Molded Underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on the void free methodology to minimize void between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding Compound (EMC) selection approach, air vent design of cavity vacuum molding, and void formation mechanism by mold flow simulation and DOE(Design of Experiment) of several SIP module layouts. The test vehicle used for this study of MUF by vacuum transfer molding shown as SiP module (8.2×7.7×1.13mm) which was sawn from 52.70×68.70×0.75mm mold area of 118.5*75.5*0.38 substrate. One segment mold inside (52.70× 68.70×0.75mm) had 35ea SiP modules (7X5 unit array). In addition, one SiP module included one Flip chip RF/BB IC(6.51×5.81×0.41mm) which had 339ea bumps and 95um Bump height, one Flip chip RF switch (0.705×0.705× 0.33mm) which had 4 bumps and 85um bump height, 1.6×0.8×0.6mm size of LC filter, and total 25ea passives. In the end, SAT result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.

Second- and Third-Level BGA Solder Joint Reliability of High-End Flip Chip System in Package (FCSiP)

The major concerns posed by system-in-package (SiP) designs for network applications are the interconnection reliability between the memory plastic ball grid array (PBGA) package and the SiP module, which we refer to as 2nd-level interconnection, and between the SiP module and the system board, which we refer to as 3rd-level interconnection, induced by thermomechanical stress to the large SiP module, i.e., 55 × 55 mm2 package body size. In this paper, finite element analysis (FEA) and design of experiment (DOE) case studies were used to evaluate the 2803-pin flip chip SiP (FCSiP) and to determine the best construction of the SiP module and optimize the assembly material set. Heat spreader (lid) thickness, heat spreader material, and under-fill implementation were considered in the stress and fatigue lifetime FEA case studies and long-term solder joint reliability, which was accelerated thermal cycle (ATC) tested at operating temperatures from 0 to 100°C. Another important factor in the system-level reliability is an external heat sink, and its compressive force effect was also investigated in the ATC test. In addition, short-term mechanical reliability tests, such as the 4-point monotonic bend test based on the IPC-9702 specification and mechanical shock test based on the JESD22-B110A standard, were also evaluated for the 2803-pin FCSiP qualification. Finally, the results of these experiments were compared with the FEA data in a correlation process.

A very compact 62‐GHz transmitter LTCC SiP module for wireless terminals applications

AbstractA 10 × 21 × 1 mm3, very compact low temperature cofired ceramic (LTCC) system‐in‐package (SiP) transmitter module is presented for future wireless terminal applications. Five GaAs monolithic microwave integrated circuits (MMIC) chipsets including a power amplifier, driver amplifier, mixer, and two frequency multipliers are integrated into a LTCC multilayer circuit for the heterodyne transmitter. The fabricated transmitter module achieves an output of 13 dBm at a RF frequency of 62 GHz, an IF frequency of 2.4 GHz, and an local oscillator frequency of 59.6 GHz. The up‐conversion gain is 11 dB; while the local oscillator signal is suppressed below −20.6 dBc with the image rejection mixer, and the image and spurious signals are also suppressed below −29.6 dBc. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 575–578, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22211