Synchronous Dynamic Random Access Memory Research Articles

Real-time FPGA Implementation of an Optic Flow Algorithm Suitable for Background Oriented Schlieren Technique

Abstract To meet the demands of real-time displacement detection in embedded systems, a real-time optical flow calculation method suitable for background oriented schlieren (BOS) technology was transplanted and implemented on an Field Programmable Gate Array(FPGA) system. Firstly, through the analysis of different optical flow operation characteristics and the comparison of processing results in MATLAB with actual experimental data, an optical flow algorithm suitable for real-time processing of background shadow images was selected. Subsequently, by using hardware pipelining and multimodule parallel processing, the single-layer L&K optical flow algorithm was transplanted onto the FPGA and algorithm optimization was performed to achieve real-time optical flow calculation based on adjacent frame images. The key optimization techniques in this paper mainly include cleverly designing Double-Data-Rate Three Synchronous Dynamic Random Access Memory (DDR3) memory partitioning read and write logic to avoid image read and write conflicts; ensuring the timing alignment and data synchronization of consecutive frames by using burst read arbitration modules and two independent First In First Out (FIFO) buffers; and in optical flow calculation, constructing a 3×3 window using a shifting FIFO method to effectively save cache resources and improve computational speed. Experimental results show that the system can achieve real-time processing speeds of not less than 60fps for 1024×768 resolution images, meeting the requirements of practical applications.

ADS-CNN: Adaptive Dataflow Scheduling for lightweight CNN accelerator on FPGAs

Lightweight convolutional neural networks (CNNs) enable lower inference latency and data traffic, facilitating deployment on resource-constrained edge devices such as field-programmable gate arrays (FPGAs). However, CNNs inference requires access to off-chip synchronous dynamic random-access memory (SDRAM), which significantly degrades inference speed and system power efficiency. In this paper, we propose an adaptive dataflow scheduling method for lightweight CNN accelerator on FPGAs named ADS-CNN. The key idea of ADS-CNN is to efficiently utilize on-chip resources and reduce the amount of SDRAM access. To achieve the reuse of logical resources, we design a time division multiplexing calculation engine to be integrated in ADS-CNN. We implement a configurable module for the convolution controller to adapt to the data reuse of different convolution layers, thus reducing the off-chip access. Furthermore, we exploit on-chip memory blocks as buffers based on the configuration of different layers in lightweight CNNs. On the resource-constrained Intel CycloneV SoC 5CSEBA6 FPGA platform, we evaluated six common lightweight CNN models to demonstrate the performance advantages of ADS-CNN. The evaluation results indicate that, compared with accelerators that use traditional tiling strategy dataflow, our ADS-CNN can achieve up to 1.29× speedup with the overall dataflow scale compression of 23.7%.

A design strategy for analyzing signal integrity in DDR3 bus of high speed embedded systems

A complex modern embedded system using a multi-core Central Processing Unit (CPU) toward a compact integrated design in a single Printed Circuit Board (PCB). One of the biggest challenges of the design is to meet the Signal Integrity for high speed Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3) bus. A typical strategy to solve the challenge is the simulation on the computer, but this is not always an effective solution as has a gap between simulation software and practical PCB. The gap is correlated to localized changes in copper density within the PCB and characterization of heterogeneous materials in PCB that could lead to differences in the real PCB. The purpose of the research presents an analysis methodology to design DDR) memory interfaces in high speed embedded systems, related to Signal Integrity and the impact of copper density on PCB trace impedances to overcome these challenges. Moreover, the presented design methodology is also applied to the next generation DDR as well as other styles of CPU.

Parameterized SDRAM-based content-addressable memory on field programmable gate array

Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besides, the collision ratio is high in FPGA-based CAMs, leading to data loss and failure to produce accurate addresses. Synchronous dynamic random-access memory (SDRAM)-based CAMs, benefiting from the features of high density and low price of SDRAM, solve the limitations of FPGA’s on-chip resources. This paper proposes a data collision CAM hardware implementation using modern FPGA’s off-chip SDRAM for data storage. The hardware architecture is customized for massive lookup tables and resource-saving. Furthermore, the architecture is parameterized, which is better for integration. The synthesis results and comparisons show significant advancement compared to other FPGA-based CAM implementations by total reduction of on-chip RAM. The novel architecture shows remarkable improvement in the memory depth and width with the capacity of 128 Mbyte lookup table.

Nonlocal Noise Removal Technique to Improve the Electromagnetic Field Pattern in Near-Field Scanning of a Device

A nonlocal noise removal technique, known as block-matching 3-D (BM3D), is introduced to improve the quality of a blurry electromagnetic pattern generated from near field of a device. Noise distribution in electromagnetic pattern is analyzed. Taking the nonlocal self-similarity into account, the BM3D technique removes the noise of the pattern in a 3-D transformation domain based on sparse representation. First, the noise removal technique was validated well on the profile recovery of weak emission of a microstrip line driven by a square wave. Then, the BM3D technique is applied to improve source localization in a field programmable gate array (FPGA) and also to improve pattern clustering in a double data rate (DDR) synchronous dynamic random access memory (SDRAM) integrated circuit (IC). Both the applications demonstrate the effectiveness of the BM3D noise removal technique in the near-field scanning patterns of a device.

Securing SoCs With FPGAs Against Rowhammer Attacks

Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications, such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch noncacheable synchronous DRAM (SDRAM) transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today’s countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, today’s countermeasures that count the frequency of activation of memory rows cannot identify the intellectual property (IP) that launches the attack from the FPGA. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes 6.3% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA, when multiple IPs are monitored.

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian Environment

This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyväskylä, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyväskylä. In these irradiation tests, stuck bits originating from electron-induced single-event effects (SEEs) were found, as well as single bit-flips from single electrons. To the best knowledge of the authors, this is the first time that stuck bits from single-electron events have been reported in the literature. It is argued in the article that the single-event bit-flips and stuck bits are caused by the same damage mechanism, which would be large displacement damage clusters, and that the two different fault modes represent different amounts of damage to the memory cell. After a large particle fluence, a rapid increase in the error rate was observed, originating from the accumulation of smaller displacement damage clusters in the memory cells. The 110-nm memory was a candidate component to fly on the European Space Agency (ESA) JUpiter ICy moons Explorer (JUICE) mission, so the SEE cross section as a function of electron energy was compared to the expected electron environment encountered by JUICE to estimate the error rates during the mission.

An Efficient FPGA-Based Implementation for Quantized Remote Sensing Image Scene Classification Network

Deep Convolutional Neural Network (DCNN)-based image scene classification models play an important role in a wide variety of remote sensing applications and achieve great success. However, the large-scale remote sensing images and the intensive computations make the deployment of these DCNN-based models on low-power processing systems (e.g., spaceborne or airborne) a challenging problem. To solve this problem, this paper proposes a high-performance Field-Programmable Gate Array (FPGA)-based DCNN accelerator by combining an efficient network compression scheme and reasonable hardware architecture. Firstly, this paper applies the network quantization to a high-accuracy remote sensing scene classification network, an improved oriented response network (IORN). The volume of the parameters and feature maps in the network is greatly reduced. Secondly, an efficient hardware architecture for network implementation is proposed. The architecture employs dual-channel Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) access mode, rational on-chip data processing scheme and efficient processing engine design. Finally, we implement the quantized IORN (Q-IORN) with the proposed architecture on a Xilinx VC709 development board. The experimental results show that the proposed accelerator has 88.31% top-1 classification accuracy and achieves a throughput of 209.60 Giga-Operations Per Second (GOP/s) with a 6.32 W on-chip power consumption at 200 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency.

A system verilog approach for verification of memory controller

<span>Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.</span>

Design and Verification of SDRAM Controller Based on FPGA

SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.

An Algorithmic Approach to Observed Single Event Effects in Van Allen Probes Solid State Recorders

A new algorithmic approach yields insights into the relationship between predicted and on-orbit synchronous dynamic random access memory (SDRAM) error rates on the Van Allen Probes. This article describes more than 5.5 years of data on Solid State Recorder Single Event Effects (SEEs) from December 4, 2012 to June 30, 2018. We compare observations with predictions from the early spacecraft design and give reasons for the large overpredictions. We analyze observed SEEs versus L-shell position and the memory device location on the Solid State Recorder electronic card. We examine the differences among the outlying SEE-susceptible devices on the two spacecraft. The inflight results demonstrate the conservatism of the predictions for the overall upset rate.

Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

Efficiency balanced matrix transpose method for sliding spotlight SAR imaging processing

Matrix transposition is a very critical operation in synthetic aperture radar (SAR) imaging systems. This study presents an improved corner turning memory solution for real-time SAR imaging processing. Based on the sub-matrix three-dimensional mapping method, the efficiency of matrix transposing is greatly increased. However, in sliding spotlight mode, a novel SAR imaging mode, the amount of raw data is increased too large to directly use the above method. In this study, a joint address mapping strategy for two pieces of double data rate 3 synchronous dynamic random-access memory is used to meet the needs of the amount of data and make up for the lack of original method. The experimental results show that this method can get an improved and balanced two-dimensional access efficiency for sliding spotlight mode SAR imaging processing.

Unaligned Burst-Aware Memory Subsystem

In this paper, we present a memory subsystem for a burst that is unaligned to a block of synchronous dynamic random access memory (SDRAM) columns. In the case that a processor demands such an unaligned burst, a memory subsystem is required to rearrange SDRAM transfers in the order demanded by the processor. Our memory subsystem modifies a memory address given by a processor, then accesses SDRAMs with the modified memory address, and thus makes SDRAMs output transfers in an intermediate order. The transfers can be rearranged in the order demanded by the processor with the minimal performance degradation. Next, urgent transfers within the burst are delivered via priority service, and nonurgent transfers within the burst can be independently delivered via best-effort service. Experimental results show that the proposed memory subsystem achieves, on average, 16.6% shorter program execution time and 13.5% shorter memory latency than a conventional memory subsystem for wrapping bursts in the case that a quadcore processor concurrently executes four benchmarks. In addition, the proposed memory subsystem achieves, on average, 5.4% shorter application execution time and 3.4% shorter memory latency than a conventional memory subsystem for incrementing bursts in case of double data rate (DDR) 3 SDRAMs.

Implementation of a camera system using nios II on the altera DE2-70 board

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.

SOC integration for video processing application

Video processing is an additional system that can improve the functionality of video surveillance. Integration of a simple video processing system into a complete camera system with a field-programmable gate array (FPGA) is an important step for research, to further improve the tracking process. This paper presents the integration of greyscale conversion into a complete camera system using Nios II software build tools for Eclipse. The camera system architecture is designed using the Nios II soft-core embedded processor from Altera. The proposed greyscale conversion system is designed using the C programming language in Eclipse. Parts of the architecture design in the camera system are important if greyscale conversion is to take place in the processing, such as synchronous dynamic random-access memory (SDRAM) and a video decoder driver. The image or video is captured using a Terasic TRDB-D5M camera and the data are converted to RGB format using the video decoder driver. The converted data are shown in binary format and the greyscale conversion system extracts and processes the data. The processed data are stored in the SDRAM before being sent to a VGA monitor. The camera system and greyscale conversion system were developed using the Altera DE2-70 development platform. The data from the video decoder driver and SDRAM were examined to confirm that the data conversion matched greyscale conversion formulae. The converted data in the SDRAM correctly displayed the greyscale image on a VGA monitor.

Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface

A parallel branching synchronous dynamic random access memory (SDRAM) channel with write-direction impedance matching (parallel branching with write-direction impedance matching (PBIM)) is proposed for an 8-drop 6.4-Gb/s SDRAM interface. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of two dual in-line memory modules for a 4-drop configuration and the data (data pin) channel uses two kinds of transmission lines with characteristic impedances of 50 and 25 Ω and a resistor on the motherboard. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gb/s in both write and read directions by using the same motherboard area as that of the stub series terminated logic channel and a bit-error-rate tester for transmitter and receiver.

FPGA-Based Real-Time Digital Solver for Electro-Mechanical Transient Simulation

A field-programmable gate array (FPGA)-based digital solver for real-time electromechanical transient simulation is designed in this paper. The solving process for a device or sub-network in an electromechanical transient simulation is packaged into the orders in soft function solvers. The orders are reused by soft function solvers that are invoked by microprocessor cores. The data exchange between the microprocessor cores and soft function solvers is enhanced through explicit and implicit channels. The orders of the microprocessor cores are stored in the synchronous dynamic random access memory on the FPGA board, which solves the problem of insufficient storage space for the orders in electromechanical transient simulation. A real-time digital solver for electromechanical transient simulation, whose feasibility is verified by a simulation of part of the power system in East China, is successfully constructed by applying a small number of microprocessor cores and multiple soft function solvers.

Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory

Due to the complexity of IC, electromagnetic immunity plays a critical role towards evaluating the EMC performance to avoid the high cost of redesign. This paper focuses on the Direct Power Injection (DPI) immunity of processor chips with different external double data rate3 (DDR3) synchronous dynamic random access memory (SDRAM) in consumer electronics. To complete the DPI test, a test board complying with the standard IEC62132-4 and a dedicated test code have been designed. The effect of DC power injection interference on same DDR model but different DDR pins and the same DDR pin but different DDR models were analysed, the results can be used to locate the system-level EMC issues and optimize the design.