Synchronous Dynamic Random Access Memory Research Articles

A seamless acquisition digital storage oscilloscope with three-dimensional waveform display

In traditional digital storage oscilloscope (DSO), sampled data need to be processed after each acquisition. During data processing, the acquisition is stopped and oscilloscope is blind to the input signal. Thus, this duration is called dead time. With the rapid development of modern electronic systems, the effect of infrequent events becomes significant. To capture these occasional events in shorter time, dead time in traditional DSO that causes the loss of measured signal needs to be reduced or even eliminated. In this paper, a seamless acquisition oscilloscope without dead time is proposed. In this oscilloscope, three-dimensional waveform mapping (TWM) technique, which converts sampled data to displayed waveform, is proposed. With this technique, not only the process speed is improved, but also the probability information of waveform is displayed with different brightness. Thus, a three-dimensional waveform is shown to the user. To reduce processing time further, parallel TWM which processes several sampled points simultaneously, and dual-port random access memory based pipelining technique which can process one sampling point in one clock period are proposed. Furthermore, two DDR3 (Double-Data-Rate Three Synchronous Dynamic Random Access Memory) are used for storing sampled data alternately, thus the acquisition can continue during data processing. Therefore, the dead time of DSO is eliminated. In addition, a double-pulse test method is adopted to test the waveform capturing rate (WCR) of the oscilloscope and a combined pulse test method is employed to evaluate the oscilloscope's capture ability comprehensively. The experiment results show that the WCR of the designed oscilloscope is 6,250,000 wfms/s (waveforms per second), the highest value in all existing oscilloscopes. The testing results also prove that there is no dead time in our oscilloscope, thus realizing the seamless acquisition.

Analysis of Blocking and Scheduling for FPGA-Based Floating-Point Matrix Multiplication Analyse du blocage et de l’ordonnancement d’une multiplication matricielle à virgule flottante sur un FPGA

This paper considers blocking and scheduling for the design and implementation of field-programmable gate array (FPGA)-based floating-point parallel matrix multiplication in the presence of a memory hierarchy. For high performance, on-chip memory holds data that are reused when the computation is divided into blocks, and multiple arithmetic units perform independent operations within each block in parallel. The first contribution of this paper is a detailed analysis of the design space to characterize performance based on the amount of on-chip memory used and the approaches considered for blocking and scheduling of the computation. A comparison is also made to prior work with a unified view. The second contribution is a flexible high-performance implementation for the Altera Stratix IV EP4SGX530C2 FPGA with an interface to external double-data-rate synchronous dynamic RAM (DDR2 SDRAM) memory. Various configuration options support optimization of different objectives, and the resulting configurations have been verified in simulation and in hardware. For double-precision floating-point, a performance of 16 giga-floating-point operations per second (GFLOPS) is achievable with 64 arithmetic units at 160 MHz.

Focus on software and data acquisition

Focus on software and data acquisition

Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor.

Configurable memory security in embedded systems

System security is an increasingly important design criterion for many embedded systems. These systems are often portable and more easily attacked than traditional desktop and server computing systems. Key requirements for system security include defenses against physical attacks and lightweight support in terms of area and power consumption. Our new approach to embedded system security focuses on the protection of application loading and secure application execution. During secure application loading, an encrypted application is transferred from on-board flash memory to external double data rate synchronous dynamic random access memory (DDR-SDRAM) via a microprocessor. Following application loading, the core-based security technique provides both confidentiality and authentication for data stored in a microprocessor's system memory. The benefits of our low overhead memory protection approaches are demonstrated using four applications implemented in a field-programmable gate array (FPGA) in an embedded system prototyping platform. Each application requires a collection of tasks with varying memory security requirements. The configurable security core implemented on-chip inside the FPGA with the microprocessor allows for different memory security policies for different application tasks. An average memory saving of 63% is achieved for the four applications versus a uniform security approach. The lightweight circuitry included to support application loading from flash memory adds about 10% FPGA area overhead to the processor-based system and main memory security hardware.

同步动态随机存储器辐射效应测试系统研制

同步动态随机存储器辐射效应测试系统研制

Low-Power Time Deinterleaver for ISDB-T Receiver

A time deinterleaver structure for Terrestrial Integrated Services Digital Broadcasting (ISDB-T) is presented to reduce power consumption in synchronous dynamic random-access memory (SDRAM). ISDB-T exploits long time interleaving, which requires many long delay buffers at the deinterleaving of the receiver. The conventional single-pointer structure reduces the number of the pointer registers, but it shows inefficiency with SDRAM. The proposed structure allocates the delay buffers appropriately for reducing the number of SDRAM accesses and row activations and, as a result, the SDRAM power consumption. Experimental result shows that SDRAM power consumption is reduced by 24%.

Heavy-Ion Radiation Characteristics of DDR2 Synchronous Dynamic Random Access Memory Fabricated in 56 nm Technology

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 <TEX>$MeVcm^2/mg$</TEX>. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

Hybrid partitioned H.264 full high definition decoder on embedded quad-core

In this paper, the problem of efficient mapping of the H.264 decoder on an embedded quad-core platform is addressed. For this purpose, a new partitioning method called `hybrid partitioning' is proposed. Partitioning is a very important issue for the mapping of application software on multi-core systems. For H.264 video decoders, functional partitioning and data partitioning were proposed, and usually used. Hybrid partitioning is the mixture of two partitioning methods, and each module is partitioned by functional partitioning or data partitioning, depending on the module's features. Compared with dedicated functional or data partitioning, hybrid partitioning is as powerful as data partitioning for load balancing between cores, and is also as efficient as functional partitioning from the viewpoint of memory requirement. Hybrid partitioning is also free from the macroblock level dependency problem that data partitioning usually has in video decoding. As a result of applying hybrid partitioning, 86.0% of waiting overhead is reduced, compared with functional partitioning. Regarding memory usage, hybrid partitioning requires 51.2% less VLIW (Very Long Instruction Word) program memory, and 62.0% less CGRA (Coarse-Grained Reconfigurable Array) program memory, than data partitioning. As for SDRAM (Synchronous Dynamic Random-Access Memory) bandwidth, compared with data partitioning, hybrid partitioning conserves the SDRAM bandwidth of 38.6MHz. This is 11.6% of the whole bandwidth budget of 333MHz SDRAM memory used in experiments. A parallelized decoder with hybrid partitioning on an embedded quad-core system is 3.5 times faster than that on a single core.

인공위성용 3차원 메모리 패키징 기술

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

Server-class DDR3 SDRAM memory buffer chip

IBM System i®, System p®, and System z® servers require an efficient ultrareliable high-performance memory subsystem. The fourth-generation IBM advanced memory buffer (AMB) chip provides industry-leading performance, scalability, and reliability for the double-data-rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) subsystems employed across a wide range of server platforms. The new IBM AMB employs a cyclic redundancy code-protected packet-protocol-based 6.4-Gb/s host channel, as well as dual 9-byte/10-byte wide 800 to 1,333-Mb/s SDRAM interfaces with dynamic calibration for optimal signal integrity under varied device and system environmental conditions. Applications support industry-standard dual inline memory module (DIMM) and low-latency high-capacity proprietary DIMM packages in conventional multichannel and redundant array of independent memory system architectures. A fully configured daisy-chain topology contains up to 256 GB of memory per host channel. This paper describes the IBM AMB chip architecture, design, and key engineering aspects.

Design of Double SDRAM Controller for Multibus Ground-Based Test Equipment

A double Synchronous Dynamic Random Access Memory controller based on ping-pong operation as the data buffer is designed to meet the requirement of large data amount and high transmission speed for multibus ground-based test equipment of a certain missile system. The design scheme which use FPGA as the main controller is presented in detail, including the internal interface of SDRAM, processings of data transmission and realization of ping-pong operation. The function of this controller is validated through the picked images from image generator, and the result shows that it can write and read data at the steady rate of 125Mbit/s, which indicate this SDRAM controller is feasible for the multibus ground-based test equipment

Application-Aware NoC Design for Efficient SDRAM Access

In systems-on-chip (SoCs), a microprocessor demands guaranteed synchronous dynamic random access memory (SDRAM) latency whereas most of the other cores are served as a best-effort packet. However, a priority service for the guaranteed latency causes the SDRAM utilization and latency of an overall system to be degraded critically. In addition, the data size of SDRAM requested by various cores is not matched with an SDRAM access granularity such that the SDRAM utilization and latency are further deteriorated. In this paper, we propose an application-aware networks-on-chip (NoCs) design for an efficient SDRAM access, which can consider memory latency demands and memory access granularities in various applications. In order to provide short latency for priority memory requests with few penalties, memory request packets are scheduled by our guaranteed SDRAM service router that includes a hybrid flow controller of priority-first and priority-equal algorithms. In addition, our SDRAM access granularity matching NoC design further improves the memory performance by splitting a memory request packet to several short memory request packets and then controlling the short memory request packets with a partially open-page mode and an auto-precharge operation in a memory subsystem. Experimental results show that our cost-effective application-aware NoC design significantly improves, on average, memory latency for latency-sensitive cores up to 32.8%, overall memory latency up to 7.8%, and memory utilization up to 3.4%, compared to the state-of-the-art SDRAM-aware NoC design .

Building Data Centers With Optically Connected Memory

Future data centers will require novel, scalable memory architectures capable of sustaining high bandwidths while still achieving low memory access latencies. Electronic interconnects cannot meet the challenges presented by the need for multi-terabit off-chip memory data paths. In this work, the electronic bus between main memory and its host processor is replaced with a circuit-switched optical interconnection network. We investigate the impact of our optically connected memory system on large-scale architectures and experimentally validate the protocol using field-programmable gate array based processor nodes and a custom-designed memory controller. The processor communicates all-optically with multiple synchronous dynamic random access memory nodes using 4 × 2.5-Gb/s wavelength-striped payloads, operating error free with bit-error rates less than 10-12.

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4×4 array, pixel size: 3 mm×3 mm) coupled 1:1 with LYSO scintillators (4×4 array, pixel size: 3 mm×3 mm×20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and then transferred to a host computer for coincidence sorting and image reconstruction. In order to evaluate the functionality of the developed signal processing method, energy and timing resolutions for brain PET were measured via the placement of a 6 μCi 22Na point source at the center of the PET scanner. Furthermore the PET image of the hot rod phantom (rod diameter: from 2.5 mm to 6.5 mm) with activity of 1 mCi was simulated, and then image acquisition experiment was performed using the brain PET. Measured average energy resolution for 1152 GAPD channels and system timing resolution were 19.5% (FWHM%) and 2.7 ns (FWHM), respectively. With regard to the acquisition of the hot rod phantom image, rods could be resolved down to a diameter of 2.5 mm, which was similar to simulated results. The experimental results demonstrated that the signal processing method developed herein was successfully implemented for brain PET. This reduced the complexity, cost and developing duration for PET system relative to normal PET electronics, and it will obviously be useful for the development of high-performance investigational PET systems.

Multidimensional DFT IP Generator for FPGA Platforms

Multidimensional (MD) discrete Fourier transform (DFT) is a key kernel algorithm in many signal processing applications. In this paper we describe an MD-DFT intellectual property (IP) generator and a bandwidth-efficient MD DFT IP for high performance implementations of 2-D and 3-D DFT on field-programmable gate array (FPGA) platforms. The proposed architecture is generated automatically and is based on a decomposition algorithm that takes into account FPGA resources and the characteristics of off-chip memory access, namely, the burst access pattern of the synchronous dynamic RAM (SDRAM). The IP generator has been integrated into an in-house FPGA development platform, AlgoFLEX, for easy verification and fast integration. The corresponding 2-D and 3-D DFT architectures have been ported onto the BEE3 board and their performance measured and analyzed. The results shows that the architecture can maintain the maximum memory bandwidth throughout the whole procedure while avoiding matrix transpose operations used in most other MD DFT implementations. To further enhance the performance, the proposed architecture is being ported onto the newly released Xilinx ML605 board. The simulation results show that 2 K × 2 K images with complex 64-bit precision can be processed in less than 27 ms.

An SDRAM-Aware Router for Networks-on-Chip

Networks-on-chip (NoCs) may interface with lots of synchronous dynamic random access memories (SDRAM) to provide enough memory bandwidth and guaranteed quality-of-service for future systems-on-chip (SoCs). SDRAM is commonly controlled by a memory subsystem that schedules memory requests to improve memory efficiency and latency. However, a memory subsystem is still a performance bottleneck in the entire NoC. Therefore, memory-aware NoC optimization has attracted considerable attention. This paper presents a NoC router with an explicit SDRAM-aware flow control. Based on priority-based arbitration, our SDRAM-aware flow controller schedules memory requests to prevent bank conflict, data contention, and short turn-around bank interleaving. Moreover, our multi-stage scheduling scheme further improves memory performance and saves NoC hardware costs. Experimental results show that our cost-efficient SDRAM-aware NoC design significantly improves memory latency and utilization compared to the conventional NoC design with no SDRAM-aware router.

Development of improved memory architecture FDTD/FIT dedicated computer based on SDRAM for large scale microwave simulation

Authors have been working in devlopment of the Finite Difference Time Domain (FDTD) / the Finite Integration Technique (FIT) dedicated computer for high performance computation of microwave simulation. Especially the dedicated computer with optimized memory access architecture was proposed to reduce overhead of Neuman bottleneck in FDTD calculation. Based on the optimized memory architecture, dedicated computer was implemented on fully customized Printed Circuit Board (PCB) by using the Field Programable Gate Array (FPGA) and asynchronous Static Random Access Memory (SRAM). This paper presents a newly developed FDTD/FIT dedicated computer based on Synchronous Dynamic Random Access Memory (SDRAM) for larger scale and higher performance simulation.

The Random Telegraph Signal Behavior of Intermittently Stuck Bits in SDRAMs

This paper reports behavior analogous to the Random Telegraph Signal (RTS) seen in the leakage currents from radiation induced hot pixels in Charge Coupled Devices (CCDs), but in the context of stuck bits in Synchronous Dynamic Random Access Memories (SDRAMs). Our analysis suggests that pseudo-random sticking and unsticking of the SDRAM bits is due to thermally induced fluctuations in leakage current through displacement damage complexes in depletion regions that were created by high-energy neutron and proton interactions. It is shown that the number of observed stuck bits increases exponentially with temperature, due to the general increase in the leakage currents through the damage centers with temperature. Nevertheless, some stuck bits are seen to pseudo-randomly stick and unstick in the context of a continuously rising trend of temperature, thus demonstrating that their damage centers can exist in multiple widely spaced, discrete levels of leakage current, which is highly consistent with RTS. This implies that these intermittently stuck bits (ISBs) are a displacement damage phenomenon and are unrelated to microdose issues, which is confirmed by the observation that they also occur in unbiased irradiation. Finally, we note that observed variations in the periodicity of the sticking and unsticking behavior on several timescales is most readily explained by multiple leakage current pathways through displacement damage complexes spontaneously and independently opening and closing under the influence of thermal vibrations.

Life cycle assessment of DRAM in Taiwan's semiconductor industry

The semiconductor industry plays a leading role in supporting economic stabilization and social progress in Taiwan. In this paper, Eco-indicator 95 and Impact 2002+ are utilized to evaluate the potential environmental impacts from five production processes of the double data rate synchronous dynamic random access memory (DDR SDRAM). The comparisons between these two impact methods and their scopes are also discussed. From our results, global warming potential and non-renewable energy consumption were identified as the major environmental impacts. Applications of Eco-indicator 95 and IMPACT 2002+ also suggest that summer smog and respiratory inorganics are significant impact categories. The comparison of the scopes of these two methods identifies that low GWP potential PFCs substitution and electricity saving are effective ways to decrease environmental impacts of DRAM manufacturing. In addition, IMPACT 2002+ is a more applicable LCA method for the semiconductor industry in Taiwan due to the structure and reference area of this method and the characteristics of the semiconductor industry in Taiwan.