Synchronous Digital Systems Research Articles

A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock

The continuous search for higher performances and low power dissipation on digital systems shows to be critical. The pipeline control is a good alternative for achieving good results, but the activity of the clock is responsible for the high consumption of 15–45% of the total circuit energy. Decreasing the clock activity leads not only to a reduction of this consumption but also to a reduction of noise and electromagnetic interference. An interesting approach to achieve this goal is the design of synchronous digital systems that operate in both edges of the clock signal (double-edge triggered – DET), allowing a reduction of 50% in the operating frequency while maintains the same data processing rate. As we know, the use of double-edge triggered flip-flops (DET-FF) leads to some main drawbacks. Then, in this paper, we propose a novel method that allows synthesizing synchronous digital systems with pipeline control. Such control operates in both edges of the clock using only standards flip-flops (single-edge triggered flip-flops-SET-FF) as components of the state memories. The method was validated for a well-known example (second order differential equation solver), and it was applied to a set of 5 well-known benchmarks, showing a mean reduction of 53% in latency time when compared to conventional methods working at the same frequency (in the case 50MHZ). We achieved an average reduction of 10% in latency time when the operating frequency of our projects was reduced to 25MHZ and compared to conventional ones at 50MHZ. The proposed method leads to a mean reduction of 45% in dynamic power consumption when compared to conventional ones. These results, although presenting a minimum area penalty, show a high potential of practical implementations focusing on low-power and high performances.

A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator

Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz—a 4 $\times $ improvement over state-of-the-art for comparable stability.

Comparison of D-flip-flops and D-latches: influence on SET susceptibility of the clock distribution network

As technology scales down, clock distribution networks (CDNs) in integrated circuits (ICs) are becoming increasingly sensitive to single-event transients (SETs). The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements (D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.

Application and Development of PTN Technology

The packet transmission network (PTN) technology, which combines the advantages of packet technology and synchronous digital system (SDH) technology, is more suitable for multi-service bearer and exchange, and satisfi es fl exible network scheduling and multi-service transmission. It can provide network protection function. PTN technical characteristics determine that he can better use the existing network, can provide more with the current network interface. This paper analyzes the characteristics of PTN technology and the existing networking methods, and proposes a network improvement method of IP + PON + PTN.

Research on the Process Layer and Substation Layer Relay Protection in Smart Substation Relay Protection

The intelligent substation relay protection facility is a fundamental element in construction of modern power system, based on the principles of flexibility, security and accuracy, and it can be divided into process layer and substation layer according to specific equipment. The former is suitable for individual sampling of disposable equipment, can be separated from the base station synchronization sampling, with the help of synchronous digital system and ping-pong algorithm to achieve synchronization of the overall sampling, that is to take the distribution protection components, through the separate transmission medium to realize the information transmission; the latter is for variable power plant components centralized backup protection, taking online real-time tuning technique.

Study on Relay Protection of Process Layer and Substation in Relay Protection of Intelligent Substation

The relay protection facilities of the intelligent substation are the basic elements of modern power system construction. Based on the principles of flexibility, safety and accuracy, it can be divided into process layer and substation layer according to specific equipment. The former is suitable for single sampling of disposable equip-ment, which can be separated from the base station synchronization sampling, with synchronous digital system and ping-pong algorithm to achieve the overall sampling of synchronization, that is, the distribution configuration to protect the various components, through a separate transmission medium to achieve information transmission; For the substation components centralized backup protec-tion, take the online real-time tuning technology.

Clock Scheme for FPGA Implementation of Globally Asynchronous Locally Synchronous Circuits

Objective: In this paper clock scheme for FPGA implementation of globally asynchronous locally synchronous circuits to achieve low power dissipation by reducing switching power consumption in a circuit is proposed. Method: Clock scheme for globally asynchronous locally synchronous (GALS) using clock divider and decoder module is evaluated. Clock divider and decoder module mainly divides a global clock into low switching rate control signals that simplifies in circuit clock management modules and reduce global clock rate. Findings: Asynchronous or clockless designs are considered as an alternative to conventional synchronous digital system design. The major advantages of asynchronous are low power consumption, better modularity, higher robustness and higher speed. Traditional Quasi-Delay-Insensitive (QDI) circuits are nearly impossible to be mapped onto commercial FPGAs. The correctness of a circuit using a bundled-data scheme depends on the assumption that the delay of each block (including logic and routing) is predictable and designers can use a delay-matching block to satisfy timing constraint. Clock divider and decoder modules does not incorporates delay matching block. Global clock is finely partition to the low rate control signals that results in low power dissipation with less complex circuitry and most importantly facilitates FPGA implementation.

Performance Evaluation of Phase Estimator Using LMS, Variable Step Size LMS and RLS Algorithm for QAM Communication Systems

Phase estimation is a problem of paramount importance in synchronous digital communication system, especially for high bit rate signaling such as QAM modulation. QAM is particularly attractive for high- throughput-efficiency application and better performance compared to PSK as size of constellation increases. Ideally, the phase estimation must be performed in a blind manner, means without using known training sequences of known transmitted symbols. To better understand, consider data is transmitted by transmitter using 8-QAM modulation. The data will be divided into symbol that consist of 3 bits per symbol and each modulated data will be placed at specific angle (−45 �� ,+45 �� , −135 �� , +135 �� in this case) (5) and transmitted through the common channel. At the receiver, it is required to know this phase angle accurately; else the demodulated data will encounter errors. Therefore, the accuracy in phase recovery is very important. Automatic equalizers use iterative techniques to estimate the optimum coefficients. To obtained a stable solution to the filter weights, it is necessary that the data be averaged to obtain stable signal statistics, or the noisy solution obtained from the noisy data must be averaged. The most robust of this class of algorithm is the Variable step size least mean square (VSSLMS) algorithm. Each iteration of this algorithm uses a noisy estimate of the error gradient to adjust the weights in the direction to reduce the average mean square error. Noisy gradient is simply the product of data vector and error scalar. The data vector is the vector of noise-corrupted channel samples residing in the equalizer filter at a given time. This paper focuses on LMS; Variable step size LMS and RLS (Recursive Least Square) based adaptive algorithms.

Algebraic Verification Method for SEREs Properties via Groebner Bases Approaches

This work presents an efficient solution using computer algebra system to perform linear temporal properties verification for synchronous digital systems. The method is essentially based on both Groebner bases approaches and symbolic simulation. A mechanism for constructing canonical polynomial set based symbolic representations for both circuit descriptions and assertions is studied. We then present a complete checking algorithm framework based on these algebraic representations by using Groebner bases. The computational experience result in this work shows that the algebraic approach is a quite competitive checking method and will be a useful supplement to the existent verification methods based on simulation.

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1],[2]. We regard neural oscillators as independent clock sources on LSIs; i.e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (< 1 GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-μm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

Reduction of power dissipation in sequential circuits

In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving.

Reduction of power dissipation in sequential circuits

In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving. Keywords: priority encoding, multi code state assignment, clock gating.

SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

An adaptive pulse-width control loop

Clock distribution and generation circuitry forms a critical component of current synchronous digital systems. Digital system clocks must not only have low jitter and low skew, but also a well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed complementary metal oxide semiconductor (CMOS) clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital (Fenghao and Svensson 2000). In this paper, we propose a pulsewidth control loop referred as adaptive pulsewidth control loop (APWCL) that adopts the same architecture as the conventional PWCL, but with two modifications. The first one relates to implementation of the pseudo inverter control stage (PICS), while the second to involvement of adaptive control loop. The first modification provides generation of output pulses during all APWCL's modes of operation and the second faster locking time. For 1.2 μm double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 100 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20% up to 80% if the loop parameters are properly chosen.

What are clock distribution networks?

In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, with in the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling, in that long global interconnect lines become signicantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.Most synchronous digital systems consist of cascaded banks of sequential registers with combinatorial logic between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. The global performance and local timing requirements are satisfied by the careful insertion of pipeline registers into equally spaced time windows to satisfy critical worst case timing constraints. The proper design of the clock distribution network ensures that these critical timing requirements are satisfied and that no race conditions exist.The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network. Interrelationships among these three subsystems of a synchronous digital system are critical to achieving maximum levels of performance and reliability.Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important area of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies.The literature in this field exists in a variety of journals and conference proceedings. Examples include the IEEE Transactions of Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE/ACM Design Automation Conference, and a host of related computer, circuits, and CAD conferences. Survey and review articles exist that summarize many of the primary results while providing background and perspective.

Going beyond worst-case specs with TEAtime

Virtually all engineers use worst-case component specifications for new system designs, thereby ensuring that the resulting product will operate under worst-case conditions. However, given that most systems operate under typical operating conditions that rarely approach the demands of worst-case conditions, building such robust systems incurs a significant performance cost. Further, classic worst-case designs do not adapt to variations in either manufacturing or operating conditions. A timing-error-avoidance prototype provides a circuit and system solution to these problems for synchronous digital systems. TEAtime has demonstrated much better performance than classically designed systems and also adapts well to varying temperature and supply-voltage conditions.

Pulse width control loop as a duty cycle corrector

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system?s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital [8]. In this paper, we propose a pulse width control loop referred as MPWCL (modified pulse width control loop) that adopts the same architecture as the conventional PWCL, but with a new pulse generator and new charge pump circuit as a constituent of the duty cycle detector. Thanks to using new building blocks the proposed pulse width control loop can control the duty cycle in a wide range, and what is more important it becomes operative in saturation region too, what provides conditional for fast locking time. For 1.2 ?m double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 133 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20 % up to 80 % if the loop parameters are properly chosen.

A clock power model to evaluate impact of architectural and technology optimizations- a summary

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock sub-system and the total system power budget is assessed.

A clock power model to evaluate impact of architectural and technology optimizations

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume at least a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock subsystem and the total system power budget is assessed.

Activity-driven clock design

In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a tradeoff between the amount of clock tree gating and the total power consumption of the clock tree. We exploit similarities in the switching activity of the clocked modules to reduce the number of clock gates. Assuming a given switching activity of the modules, we propose three novel activity-driven problems: a clock tree construction problem, a clock gate insertion problem, and a zero-skew clock gate insertion problem. The objective of these problems is to minimize the system's power consumption by constructing an activity-driven clock tree. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We also propose an exact algorithm employing the dynamic programming paradigm to solve the gate insertion problems. Finally, we present experimental results that verify the effectiveness of our approach. This paper is a step in understanding how high-level decisions (e.g., behavioral design) can affect a low-level design (e.g., clock design).