An adaptive pulse-width control loop

Abstract

Clock distribution and generation circuitry forms a critical component of current synchronous digital systems. Digital system clocks must not only have low jitter and low skew, but also a well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed complementary metal oxide semiconductor (CMOS) clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital (Fenghao and Svensson 2000). In this paper, we propose a pulsewidth control loop referred as adaptive pulsewidth control loop (APWCL) that adopts the same architecture as the conventional PWCL, but with two modifications. The first one relates to implementation of the pseudo inverter control stage (PICS), while the second to involvement of adaptive control loop. The first modification provides generation of output pulses during all APWCL's modes of operation and the second faster locking time. For 1.2 μm double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 100 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20% up to 80% if the loop parameters are properly chosen.