Synchronous Digital Systems Research Articles

A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs

This paper will describe a systematic method to map synchronous digital systems into dynamically reconfigurable programmable logic (i.e., programmable logic able to swap in real time the configuration defining the functionality of the system). The method is based on a temporal bipartitioning technique that is able to separate the static implementation of a circuit in two temporal independence hardware contexts. As the experimental results show, the method is capable of improving the functional density of the dynamic implementation with respect to the static one.

FIR parity check codes

This paper describes a method for packet synchronization and error detection for use in a synchronous digital communications system. The method relies upon a class of linear block codes that have parity checks that are expressed in terms of a finite-impulse response (FIR) filter. This system is incorporated in the newly established ITU standard of digital cable television standard, J.83 appendix B, which is based on an MPEG 2 transport packet data stream. This technique is also the basis for cable modem downstream transmission defined in the IEEE 802.14 and MCNS standards. The parity check structure is based on a pseudonoise sequence generated by a (binary) primitive polynomial. This structure allows for a computationally efficient implementation of the parity check FIR filter, in a recursive manner, that is none the less self-synchronizing. The FIR parity check codes that are described are characterized as the dual of a CRC-type, shortened cyclic code. The theory and computational structure of these codes are presented here; the J.83R code is used as an example of the general theory.

Short-term frequency stability of RSFQ ring oscillators

The temporal stability of the clock signal has a profound effect on the performance of synchronous RSFQ digital systems. Short-term clock fluctuations, or clock jitter, can severely degrade system performance due to the hazard of timing constraint violations. Successful large-scale RSFQ digital systems will require highly stable multi-Gigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. In this paper we identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We have developed experimental techniques for the measurement of this figure of merit and applied it to the characterization of an RSFQ ring oscillator. The experimental results are compared with results from a stochastic circuit simulator. We determined the value of jitter to be 1.52% at 10 GHz.

Faster maximum and minimum mean cycle algorithms for system-performance analysis

Maximum and minimum mean cycle problems are important problems with many applications in performance analysis of synchronous and asynchronous digital systems including rate analysis of embedded systems, in discrete-event systems, and in graph theory. Karp's algorithm is one of the fastest and most common algorithms for these problems. We present this paper mainly in the context of the maximum mean cycle problem. We show that Karp's algorithm processes more nodes and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new graph-unfolding scheme that remedies this deficiency and leads to two faster algorithms with different characteristics. Theoretical analysis tells us that our algorithms always run faster than Karp's algorithm and that they are among the fastest to date. Experiments on small benchmark graphs confirm this fact for most of the graphs. These algorithms have been used in building a framework for analysis of timing constraints for embedded systems.

27-GHz bandwidth high-speed monolithic integrated optoelectronic photoreceiver consisting of a waveguide fed photodiode and an InAlAs/InGaAs-HFET traveling wave amplifier

A monolithic integrated photoreceiver for 1.55-/spl mu/m wavelength has been designed for operation in a 20-Gb/s synchronous digital hierarchy system (SDH/SONET), based on a new integration concept. The optoelectronic integrated circuit (OEIC) receiver combines a waveguide-integrated PIN-photodiode and a traveling wave amplifier in coplanar waveguide layout with four InAlAs/InGaAs/InP-HFETs (0.7-/spl mu/m gate length). The receiver demonstrates a bandwidth of 27 GHz with a low frequency transimpedance of 40 dB/spl Omega/. This is, to our knowledge, the highest bandwidth ever reported for a monolithic integrated photoreceiver on InP. Furthermore, a receiver sensitivity of -12 dBm in the fiber (20 Gb/s, BER=10/sup -9/) and an overall optical input dynamic range of 27 dB is achieved. Optical time domain multiplex (TDM) system experiments of the receiver packaged in a module show an excellently shaped eye pattern for 20 Gb/s and an overall sensitivity of -30.5 dBm (BER=10/sup -9/) [including erbium doped fiber amplifiers (EDFA)].

High Performance Clock Distribution Networks

As semiconductor technologies operate at increasingly higher speeds, system performance has become limited not by the delays of the individual logic elements and interconnect but by the ability to synchronize the flow of the data signals. Different synchronization strategies have been considered, ranging from completely asynchronous to fully synchronous. However, the dominant synchronization strategy within industry will continue to be fully synchronous clocked systems. Systems ranging in size from medium scale circuits to large multimillion transistor microprocessors and ultra-high speed supercomputers utilize fully synchronous operation which require high speed and highly reliable clock distribution networks. Distributing the clock signals within these high complexity, high speed processors is one of the primary limitations to building high performance synchronous digital systems. Greater attention is therefore being placed on the design of clock distribution networks for large VLSI-based systems.

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations

An integrated top-down design system is presented in this paper for synthesizing clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circuit, and used to determine a non-zero clock skew schedule which reduces the clock period as compared to zero skew-based approaches. Concurrently, the permissible range of clock skew for each local data path is calculated to determine the maximum allowed variation of the scheduled clock skew such that no synchronization failures occur. The choice of clock skew values considers several design objectives, such as minimizing the effects of process parameter variations, imposing a zero clock skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value. The clock skew schedule and the worst case variation of the primary process parameters are used to determine the hierarchical topology of the clock distribution network, defining the number of levels and branches of the clock tree and the delay associated with each branch. The delay of each branch of the clock tree is physically implemented with distributed buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and the characteristics of the clock tree interconnect. A bottom-up approach for calculating the worst case variation of the clock skew due to process parameter variations is integrated with the top-down synthesis system. Thus, the local clock skews and a clock distribution network are obtained which are more tolerant to process parameter variations. This methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide clock frequency of up to 43% as compared with zero clock skew implementations are shown. Furthermore, examples of clock distribution networks that exploit intentional localized clock skew are presented which are tolerant to process parameter variations with worst case clock skew variations of up to 30%.

A clock distribution scheme for large RSFQ circuits

A primary issue in maximizing the performance of large scale synchronous digital systems is the clock distribution scheme. We present novel clocking scheme, developed specifically for RSFQ logic, which is based on the concurrent flow of the clock and data signals. The scheme permits the circuit throughput to be independent of inter-cell connection delays and significantly reduces the dependence of the throughput on the clock-to-output delay of the cells. Concurrent flow clocking is particularly well for structured architectures. The simulated maximum clock frequency of an RSFQ decimation digital filter currently under development at the University of Rochester can be as much as seven times higher using concurrent-flow clocking rather than conventional (counterflow) clocking. This advantage, however, is reduced to a factor of two due to fabrication parameter variations in present day superconductive technologies. >

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits

Timing simulation is a widely used method to verify the timing behavior of a design. In a synchronous digital system the timing property that needs to be verified is that there is no event at the outputs of the combinational parts of the circuit at or after time /spl tau/, the clock period. In this paper we first show that conventional timing simulation applied to this problem has exponential complexity. Next we demonstrate that for this problem a complete history of circuit activity before time /spl tau/ is not needed. We exploit this observation and present an event suppression method that potentially leads to an exponential reduction in the number of events that need to be processed during simulation. This is backed by encouraging experimental results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components. >

A single-phase two frequency clocking scheme for race-free glitch-free outputs of synchronous digital systems

A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 μm CMOS gate array ASICs, designed using VINYAS CAD tools.

Japan's network evolution relies on SDH-based systems

The commercial introduction of optical transmission systems based on the synchronous digital hierarchy (SDH) systems by Nippon Telephone and Telegraph is discussed. SDH-based systems efficiently multiplex signals, from narrowband telephone and facsimile signals to broadband video signals. All digital sources are synchronized regardless of their signal speed. The transmission system design concept, including the synchronous digital transmission system's modular structure that allows its functions to be freely increased and enhanced, and the SDH-based system deployment are described. >

Timing recovery in isdn U‐interface with 2B1Q line code

Abstract Timing recovery is a crucial function in synchronous digital communication systems when extracting a proper sampling phase from the received pulses. This paper describes a timing recovery method for an integrated services digital network (ISDN) U‐interface with 80 kbaud 2B1Q code. In this method, the sampling rate is equal to the symbol rate. A shaping filter is introduced to make the recovered timing phase have zero precursor to suppress the precursor intersymbol interference. The timing jitter is reduced by using a sequential filter. Computer simulations for joint operation of a decision feedback equalizer and the timing recovery circuit are performed.. The results indicate that this method is satisfactory and is not susceptible to bridged‐taps reflections. A hardware implementation of the timing recovery circuit using programmable logic arrays is completed to demonstrate the feasibility of this method.

Pipelining of high performance synchronous digital systems

A new approach is described to the design of those synchronous digital systems in which the performance parameters latency and clock frequency are of primary importance. Specifically, the trade-off between clock frequency and latency is analysed in terms of the circuit characteristics of a pipelined data path. A design paradigm relating latency and clock frequency as a function of the level of pipelining is described for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems from which the optimal level of pipelining can be determined in terms of the delays of logic, interconnect, and registers, and the clock skew and number of logic stages.

Clock frequency and latency in synchronous digital systems

The tradeoffs in the design of synchronous digital systems between clock frequency and latency in terms of the circuit characteristics of a pipelined data path are described. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, registers, clock skew, and the number of logic states. These results provide an approach to the design of those synchronous digital systems in which latency and clock frequency are of primary importance. From the behavioral specifications for the proposed system, the designer can use these results to select the best logic architecture and the best available device technology to determine if the performance specifications can be satisfied, and, if so, what design options are available for optimization of other system attributes, such as area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Obtaining schedules for digital systems

A systematic technique is presented to derive correct schedules for a synchronous digital system, given a signal flow graph for an algorithm. It is also shown how to use this technique to derive designs that are optimal in having the lowest latency, the highest throughput, or the smallest number of registers. The same technique can also be used to verify digital systems that have already been designed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Impact of long periods of identical bits on the choice of a scrambler for SDH

AbstractThe statistical properties of sequences of consecutive identical bits at the output of various scrambler types are analyzed and discussed in order to provide designers of Synchronous Digital Hierarchy systems with a wide range of choices for scrambling implementation.

Synchronous digital transmission systems based on CCITT SDH standard

The synchronous digital hierarchy (SDH) transmission systems developed by NTT are discussed. The advantages of SDH are detailed, stressing its simplified network structure and enhanced operations, administration, and maintenance functions. The layered architecture of the SDH systems is described. NTT's SDH fiber-optic transmission systems and digital radio transmission systems are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Clock skew optimization

Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS. >

An Ideal Simulator for Hardware

The increase in the density of integrated circuits has raised the level of designs that can be implemented on a single chip. Consequently, CAD tools involved in these designs have to address issues ranging from system level to logic level design. This paper presents a new hardware description language, IDEAL, and the simulation strategy adopted for it. IDEAL, which forms the basis of the Integrated Design Automation System (IDEAS) project, supports hierarchical and modular descriptions of asynchronous and synchronous digital systems at various levels. The simulator for IDEAL is based on the coroutine model. A design is simulated by appropriately scheduling coroutines which model the design entities whose behaviours given in IDEAL. Translation of a behaviour into a coroutine involves the compilation of IDEAL's data transfer and data control constructs into ‘C’.