Abstract
Abstract Timing recovery is a crucial function in synchronous digital communication systems when extracting a proper sampling phase from the received pulses. This paper describes a timing recovery method for an integrated services digital network (ISDN) U‐interface with 80 kbaud 2B1Q code. In this method, the sampling rate is equal to the symbol rate. A shaping filter is introduced to make the recovered timing phase have zero precursor to suppress the precursor intersymbol interference. The timing jitter is reduced by using a sequential filter. Computer simulations for joint operation of a decision feedback equalizer and the timing recovery circuit are performed.. The results indicate that this method is satisfactory and is not susceptible to bridged‐taps reflections. A hardware implementation of the timing recovery circuit using programmable logic arrays is completed to demonstrate the feasibility of this method.
Published Version
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