High Performance Clock Distribution Networks

Abstract

As semiconductor technologies operate at increasingly higher speeds, system performance has become limited not by the delays of the individual logic elements and interconnect but by the ability to synchronize the flow of the data signals. Different synchronization strategies have been considered, ranging from completely asynchronous to fully synchronous. However, the dominant synchronization strategy within industry will continue to be fully synchronous clocked systems. Systems ranging in size from medium scale circuits to large multimillion transistor microprocessors and ultra-high speed supercomputers utilize fully synchronous operation which require high speed and highly reliable clock distribution networks. Distributing the clock signals within these high complexity, high speed processors is one of the primary limitations to building high performance synchronous digital systems. Greater attention is therefore being placed on the design of clock distribution networks for large VLSI-based systems.