Quadratic deferred-merge embedding algorithm for zero skew clock distribution network

Abstract

Design of clock distribution networks (CDNs) in SoCs is one of the critical aspects in the realization of high performance products. Traditionally, the CDNs are generated based on binary tree data structure. However, this approach has it own limitations in terms of silicon utilization, power dissipation and latency. In this paper we propose to migrate to a quadrature tree data structure in order to gain more flexibility in locating the Steiner nodes, that can be used to minimize the CDN wire length. The quadratic data structure is applied to the Deferred-Merge Embedding algorithm (DME) where the results show that the total wire length of the CDN can be reduced effectively as the number of clock pins increases. For CDNs of 256, 1024, 4096, 16384 and 65536 clock pins, the proposed technique can reduce the CDNs total wire length by 1.85%, 3.48%, 9.2%, 23.7% and 40.3% respectively with an insignificant increase in run time. Also, using the Quadratic structure helped reducing the clock delay and the total wire elongation lengths required to achieve Zero Skew CDN.