Reduction of power dissipation in sequential circuits

B I Neelgar

doi:10.17485/ijst/2008/v1i3/10

Abstract

In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving. Keywords: priority encoding, multi code state assignment, clock gating.

Highlights

Modern digital systems are designed with a target clock period, which determines the rate of data processing
In low-power synchronous systems, it is feasible to minimize the total power consumed by the clock tree subject to performance constraints on the clock signal, such as the operating frequency and maximum clock skew
The power consumed by Complementary Metal Oxide Semiconductor (CMOS) circuits consists of two components: Dynamic power dissipation and Static power dissipation

Summary

Introduction

Modern digital systems are designed with a target clock period (or clock frequency), which determines the rate of data processing. A clock network distributes the clock signal from the clock generator, or source, to the clock inputs or sinks of the synchronizing components, or modules. The clock distribution network consumes large percentage (20%–50%) of the power consumed by these systems.

Results

Conclusion