Synchronous Dataflow Research Articles

Execution Trace--Driven Energy-Reliability Optimization for Multimedia MPSoCs

Multiprocessor systems-on-chip (MPSoCs) are becoming a popular design choice in current and future technology nodes to accommodate the heterogeneous computing demand of a multitude of applications enabled on these platform. Streaming multimedia and other communication-centric applications constitute a significant fraction of the application space of these devices. The mapping of an application on an MPSoC is an NP-hard problem. This has attracted researchers to solve this problem both as stand-alone (best-effort) and in conjunction with other optimization objectives, such as energy and reliability. Most existing studies on energy-reliability joint optimization are static—that is, design time based. These techniques fail to capture runtime variability such as resource unavailability and dynamism associated with application behaviors, which are typical of multimedia applications. The few studies that consider dynamic mapping of applications do not consider throughput degradation, which directly impacts user satisfaction. This article proposes a runtime technique to analyze the execution trace of an application modeled as Synchronous Data Flow Graphs (SDFGs) to determine its mapping on a multiprocessor system with heterogeneous processing units for different fault scenarios. Further, communication energy is minimized for each of these mappings while satisfying the throughput constraint. Experiments conducted with synthetic and real SDFGs demonstrate that the proposed technique achieves significant improvement with respect to the state-of-the-art approaches in terms of throughput and storage overhead with less than 20% energy overhead.

State-based real-time analysis of SDF applications on MPSoCs with shared communication resources

The timing predictability of Multi-Processor System on Chip (MPSoC) platforms with hard real-time applications is much more challenging than that of traditional platforms due to their large number of shared processing, communication and memory resources. Yet, this is an indispensable challenge for guaranteeing their safe usage in safety critical domains (avionics, automotive).In this article, a real-time analysis based on model-checking is proposed. The model-checking based method allows guaranteeing timing bounds of multiple Synchronous Data Flow Application (SDFA) implementations. This approach utilizes timed automata (TA) as a common semantic model to represent WCET of software components (SDF actors) and shared communication resource access protocols for buses, DMA, private local and shared memories of the MPSoC. The resulting network of TA is analyzed using the UPPAAL model-checker for providing safe timing bounds of the implementation. Furthermore, we will show the extension of our previous system model enabling single-beat inter-processor communication style beside the burst-transfer style and provide the implementation of the complete set of TA templates capturing the considered system model.We demonstrate our approach using a multi-phase electric motor control algorithm (modeled as SDFA) mapped to Infineon's TriCore-based Aurix multicore hardware platform with both the burst and single-beat inter-processor communication styles. Our approach shows a significant precision improvement (up to a percentage improvement of 300%) compared with the worst-case bound calculation based on a pessimistic analytical upper-bound delays for every shared resource access. In addition, scalability is examined to demonstrate analysis feasibility for small parallel systems, up to 40 actors mapped to 4-tiles and up to 96 actors on a 2-tiles platforms.

Comments on “Minimizing Buffer Requirements Under Rate-Optimal Schedule in Regular Dataflow Networks”

In this paper we propose a new approach that allows one to argue and discuss the results achieved so far by [7], which investigate the minimizing buffer requirements under rate-optimal schedule in Regular Dataflow Networks. Our methodology is devoted to the construction of static schedules for Digital Signal Processing Systems presented by Synchronous Dataflows (SDF) with different rates (known as Multi Rate Dataflows) and to foreseen the total amount of buffer memory of SDFs along with per arc space allocation. In [6], Govindarajan et al. call this type of dataflows Regular Stream Flow Graphs to highlight the nature of the token flow in the arcs. The mapping proposed in [11] can be seen as a natural bridge between the two domains (Petri nets and Dataflows) in investigating the buffer memory requirements, moreover one can also measure the activity duration’s on the Petri net side. The limited resource of a system is a natural issue and the claim for their availability during system’s activity must be foreseen to preclude exhaustion of resources. Therefore this occurrence inhibits system evolution and blocks it. The paper is divided in four topics. After a summarized overview of the supporting formalisms being investigated by the authors (dataflows and Petri nets), Section 2.2. addresses the main topics behind the mapping bridge outlined between dataflows and Petri nets, followed by a summarized overview of the tools and computational environments used to develop and simulate the resulting Petri net models. In Section 3, the discussion and results achieved so far are point out and used to identify misjudgment concerning the total buffer requirement for a schedule in Synchronous Dataflows. And finally in Section 4. conclusions are highlighted to emphasize the added contribution about the foreseen memory requirements for SDFs using the proposed approach by Rocha et al. [11].

High-level design space exploration for adaptive applications on multiprocessor systems-on-chip

This paper presents an abstract design and analysis framework for applications on multiprocessor systems-on-chip (MPSoCs). The aim is to allow for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support to deal with important design decisions in the early design stage. Our framework enables design space exploration in order to identify adequate parallelism levels for hardware/software mappings in presence of adaptive system behaviors. For this purpose, we use an activation clock-based encoding in which an application is represented according to its event occurrences with their precedence relations. Then, different mapping and scheduling scenarios of applications on MPSoC are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. A number of experiments are performed to compare with state-of-the-art techniques based on synchronous dataflow graphs. Experimental results show that our framework provides a similar level of precision and efficiency. In addition, our framework is more flexible to deal with both application and platform adaptive behaviors, while allowing customized communication and computation behavior simulations.

Design and Optimization of Multiclocked Embedded Systems Using Formal Techniques

Today's system-on-chip and distributed systems are commonly equipped with multiple clocks. The key challenge in designing such systems is that two situations have to be captured and evaluated in a single framework. The first is the heterogeneous control-oriented and data-oriented behaviors within one clock domain, and the second is the asynchronous communications between two clock domains. In this paper, we propose to use timed automata and synchronous dataflow to model the dynamic behaviors of the multiclock train-control system, and a multiprocessor architecture for the implementation from our model to the real system. Data-oriented behaviors are captured by synchronous dataflow, control-oriented behaviors are captured by timed automata, and asynchronous communications of the interclock domain can be modeled as an interface timed automaton or a synchronous dataflow module. The behaviors of synchronous dataflow are interpreted by some equivalent timed automata to maintain the semantic consistency of the mixed model. Then, various functional properties that are important to guarantee the correctness of the system can be simulated and verified within the framework. We apply the framework to the design of a control system described in the standard IEC 61 375 and several bugs are detected. The bugs in the standard have been fixed, and the new version has been implemented and used in the real-world subway communication control system.

Data Intensive Computing: From Modeling to Implementation

Data intensive computing encompasses applications that mostly perform data processing in regular patterns. Traditionally, such applications have been found, e.g., in image processing, audio processing, telecommunications and radar signal processing. With the immense growth of the mobile consumer electronics market, data intensive computing is present in billions of devices. In contrast to general-purpose computing, the regularity of data intensive computing enables intelligent design choices to be made in specification, modeling, design space exploration, software design, compilation and hardware design. However, unlike classic signal processing, contemporary data intensive applications, such as a H.265 video decoding or cognitive radio radio systems cannot be described with fully static representations. This dynamic nature of contemporary data intensive applications has its implications to all layers of system design, from higher-level software to hardware implementation. This special issue covers topics from the whole spectrum of design aspects for data intensive computing. Included are three articles that address dataflow specification and analysis of applications, four articles that address programmable processing hardware for data intensive applications and one publication that deals with both software and hardware design aspects. Article Parameterized Sets of Dataflow Modes and Their Application to Implementation of Cognitive Radio Systems (doi:10.1007/s11265-014-0938-4) presents a novel dataflow modeling technique named parameterized sets of modes (PSM) that addresses the important issue of modeling reconfigurable data intensive systems. After presenting a formal definition of the new concept, a cognitive radio application example is presented. Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs (doi:10.1007/ s11265-014-0952-6) is an article that concentrates on the memory usage analysis and optimization of applications that target MPSoC platforms. The application is modeled with the well-known Synchronous Dataflow formalism, based on which the memory usage analysis and optimization is performed. Experiments are performed with several data intensive applications on Intel and Texas Instruments DSP multicores. The paperModeling Resolution of Resources Contention in Synchronous Data Flow Graphs (doi:10.1007/s11265-0140923-y) addresses interprocessor communication contention on multicore platforms. The proposed approach uses Synchronous Dataflow graphs to model applications and to perform the resource contention analysis. Experiments consist from random application graphs to well-known data intensive applications, such as video and audio codecs. When going towards the hardware implementation level, issues such as processor instruction-set architectures suitable for data intensive computing become of interest. To this end, Code Density and Energy Efficiency of Exposed Datapath Architectures (doi:10.1007/s11265-014-0924-x) gives an overview of an instruction-set design direction where nontraditional aspects of the datapath are exposed to the control of the programmer in order to improve energy efficiency and instruction-level parallelism. The article looks at several proposed variations of the so called exposed datapath architectures with focus on their instruction word width overheads. A Low Energy Wide SIMD Architecture with Explicit Datapath (doi:10.1007/s11265-014-0950-8) proposes a dataoriented processor architecture which exposes the bypass P. Jaaskelainen (*) Tampere University of Technology, Tampere, Finland e-mail: pekka.jaaskelainen@tut.fi

A multi-criteria policy set optimisation framework for large-scale simulation models

Simulation modelling is an analysis approach utilised in nearly every domain for analysis of large and complex systems. Synchronous data flow (SDF) is used to model systems whose data does not follow the predetermined global schedule of discrete event simulation modelling techniques. A policy set optimisation (PSO) problem for any simulation model is the selection of a small set of controllable inputs for manipulation by a decision maker (DM) in order to achieve a desired goal. This is a multi-criteria decision making problem and a large-scale SDF simulation model creates a complex mathematical model for solution. Our PSO framework and associated procedure aims to generate the policies that will provide an estimation of the Pareto optimal solutions for the simulation model using only pre-processed model sampling. Our solution methodologies for the PSO problem aims to minimise the computation time required from the point at which a DM selects the outcomes of interest, to when they receive solution policies to choose from. This paper provides a sample problem and a discussion about the quality of the solution found.

Synthesizing Modular Invariants for Synchronous Code

In this paper, we explore different techniques to synthesize modular invariants for synchronous code encoded as Horn clauses. Modular invariants are a set of formulas that characterizes the validity of predicates. They are very useful for different aspects of analysis, synthesis, testing and program transformation. We describe two techniques to generate modular invariants for code written in the synchronous dataflow language Lustre. The first technique directly encodes the synchronous code in a modular fashion. While in the second technique, we synthesize modular invariants starting from a monolithic invariant. Both techniques, take advantage of analysis techniques based on property-directed reachability. We also describe a technique to minimize the synthesized invariants.

Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs

The majority of applications, ranging from the low complexity to very multifaceted entities requiring dedicated hardware accelerators, are very well suited for Multiprocessor Systems-on-Chips (MPSoCs). It is critical to understand the general characteristics of a given embedded application: its behavior and its requirements in terms of MPSoC resources. This paper presents a complete method to study the important aspect of memory characteristic of an application. This method spans the theoretical, architecture-independent memory characterization to the quasi optimal static memory allocation of an application on a real shared-memory MPSoCs. The application is modeled as an Synchronous Dataflow (SDF) graph which is used to derive a Memory Exclusion Graph (MEG) essential for the analysis and allocation techniques. Practical considerations, such as cache coherence and memory broadcasting, are extensively treated. Memory footprint optimization is demonstrated using the example of a stereo matching algorithm from the computer vision domain. Experimental results show a reduction of the memory footprint by up to 43 % compared to a state-of-the-art minimization technique, a throughput improvement of 33 % over dynamic allocation, and the introduction of a tradeoff between multicore scheduling flexibility and memory footprint.

데이터 플로우 기반 응용들을 위한 GPU 스케줄링 프레임워크

Recently, general purpose graphic processing units(GPUs) are being widely used in mobile embedded systems such as smart phone and tablet PCs. Because of architectural limitations of mobile GPGPUs, only a single program is allowed to occupy a GPU at a time in a non-preemptive way. As a result, it is difficult to meet performance requirements of applications such as frame rate or response time if applications running on a GPU are not scheduled properly. To tackle this difficulty, we propose to specify applications using synchronous data flow model of computation such that applications are formed with edges and nodes. Then nodes of applications are scheduled onto a GPU unlike conventional scheduling an application as a whole. This approach allows applications to share a GPU at a finer granularity, node (or task)-level, providing several benefits such as eliminating need for manually partitioning applications and better GPU utilization. Furthermore, any scheduling policy can be applied in response to the characteristics of applications.

Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing

Parallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous Dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) -- PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a software defined radio benchmark on a state-of-the-art multicore DSP platform.

Cognitive Sensor Platform

This paper describes a platform that is used to build embedded sensor systems for low energy implantable applications. One of the key characteristics of the platform is the ability to reason about the environment and dynamically modify the operational parameters of the system. Additionally the platform provides to ability to compose application specific sensor systems using a novel computational element that directly supports a synchronous-dataflow (SDF) programming paradigm. Cognition in the context of a sensor platform is defined as the “process of knowing, including aspects of awareness, perception, reasoning, and judgment”. DOI: http://dx.doi.org/10.11591/ijece.v4i4.5680

Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs

Synchronous Data Flow graphs are widely adopted in the designing of streaming applications, but were originally formulated to describe only how an application is partitioned and which data are exchanged among different tasks. Since Synchronous Data Flow graphs are often used to describe and evaluate complete design solutions, missing information (e.g., mapping, scheduling, etc.) has to be included in them by means of further actors and channels to obtain accurate evaluations. To address this issue preserving the simplicity of the representation, techniques that model data transfer delays by means of ad-hoc actors have been proposed, but they model independently each communication ignoring contentions. Moreover, they do not usually consider at all delays due to buffer contentions, potentially overestimating the throughput of a design solution. In this paper a technique to extend Synchronous Data Flow graphs by adding ad-hoc actors and channels to model resolution of resources contentions is proposed. The results show that the number of added actors and channels is limited but that they can significantly increase the Synchronous Data Flow graph accuracy.

Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems

As the number of processors in a chip increases and more functions are integrated, the system status will change dynamically due to various factors such as the workload variation, QoS requirement, and unexpected component failure. A typical method to deal with the dynamics of the system is to decide the mapping decision at runtime, based on the local information of the system status. It is very challenging to guarantee any real-time performance of a certain application in such a dynamically varying system. To solve this problem, we propose a hybrid specification of dataflow and FSM models to specify the dynamic behavior of a system distinguishing inter- and intra-application dynamism. At the top level, each application is specified by a dataflow task and the dynamic behavior is modeled as a control task that supervises the execution of applications. Inside a dataflow task, we specify the dynamic behavior using a similar way as FSM-based SADF in which an application is specified by a synchronous dataflow graph for each mode of operation. It enables us to perform compile-time scheduling of each graph to maximize the throughput varying the number of allocated processors, and store the scheduling information. When a change in system state is detected at runtime, the number of allocated processors to the active tasks is determined dynamically utilizing the stored scheduling information of those tasks in order to meet the real-time requirements. The proposed technique is implemented in the HOPES design environment. Through preliminary experiments with a simple smartphone example, we show the viability of the proposed methodology.

Worst-case Throughput Analysis for Parametric Rate and Parametric Actor Execution Time Scenario-Aware Dataflow Graphs

Scenario-aware dataflow (SADF) is a prominent tool for modeling and analysis of dynamic embedded dataflow applications. In SADF the application is represented as a finite collection of synchronous dataflow (SDF) graphs, each of which represents one possible application behaviour or scenario. A finite state machine (FSM) specifies the possible orders of scenario occurrences. The SADF model renders the tightest possible performance guarantees, but is limited by its finiteness. This means that from a practical point of view, it can only handle dynamic dataflow applications that are characterized by a reasonably sized set of possible behaviours or scenarios. In this paper we remove this limitation for a class of SADF graphs by means of SADF model parametrization in terms of graph port rates and actor execution times. First, we formally define the semantics of the model relevant for throughput analysis based on (max,+) linear system theory and (max,+) automata. Second, by generalizing some of the existing results, we give the algorithms for worst-case throughput analysis of parametric rate and parametric actor execution time acyclic SADF graphs with a fully connected, possibly infinite state transition system. Third, we demonstrate our approach on a few realistic applications from digital signal processing (DSP) domain mapped onto an embedded multi-processor architecture.

An agent-based solution for dynamic multi-node wavefront balancing in biological sequence comparison

Many parallel and distributed strategies were created to reduce the execution time of bioinformatics algorithms. One well-known bioinformatics algorithm is the Smith–Waterman, that may be parallelized using the wavefront method. When the wavefront is distributed across many heterogeneous nodes, it must be balanced to create a synchronous data flow. This is a very challenging problem if the nodes have variable computational power. This paper presents an agent-based solution for parallel biological sequence comparison applications that use the multi-node wavefront method. In our approach, autonomous agents are able to identify unbalanced computations and dynamically rebalance the load among the nodes. Two strategies were developed to the balancer agent in order to identify if the computations are balanced, one using global information and other using only local information. The global strategy demands a huge amount of data transfers, incurring in more communication, whereas the local strategy can decide about the balancing status using only local information. The results show that the balancing gains of strategies are very close. Thus, the local strategy is preferred, since it can be implemented in real wavefront balancers with almost the same benefits as the global strategy.

A Dataflow Programming Language and its Compiler for Streaming Systems

The dataflow programming paradigm shows an important way to improve programming productivity for streaming systems. In this paper we propose COStream, a programming language based on synchronous data flow execution model for data-driven application. We also propose a compiler framework for COStream on general-purpose multi-core architectures. It features an inter-thread software pipelining scheduler to exploit the parallelism among the cores. We implemented the COStream compiler framework on x86 multi-core architecture and performed experiments to evaluate the system.

Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors

In this article, we propose a heuristic algorithm for scheduling synchronous data flow (SDF) models on scratch pad memory (SPM) enhanced processors with the objective of minimizing its steady-state execution time. The task involves partitioning the limited on-chip SPM for actor code and data buffer, and executing actors in such a manner that the physical SPM is time shared with different actors and buffers (formally defined as code overlay and data overlay, respectively). In our setup, a traditional minimum buffer schedule could result in very high code overlay overhead and therefore may not be optimal. To reduce the number of direct memory access (DMA) transfers, actors need to be grouped into segments. Prefetching of code and data overlay that overlaps DMA transfers with actor executions also need to be exploited. The efficiency of the our heuristic was evaluated by compiling ten stream applications onto one synergistic processing engine (SPE) of an IBM Cell Broadband Engine. We compare the performance results of our heuristic approach with a minimum buffer scheduling approach and a 3-stage ILP approach, and show that our heuristic is able to generate high quality solutions with fast algorithm run time.

Evaluation of Speculation in Out-of-Order Execution of Synchronous Dataflow Networks

Dataflow process networks are a convenient formalism for implementing robust concurrent systems that has been successfully used for hardware and software systems in the past. However, the strictly stream-based execution limits the performance of dataflow process networks and requires to carefully balance the entire execution to avoid backpressure and idle nodes. Inspired by related techniques used in processor architectures, we already introduced in our previous work out-of-order execution of dataflow process networks. In this paper, we extend this improvement with speculation of input values for process nodes and allow otherwise idle processes to start computations with speculated input values. Clearly, outputs based on speculated inputs have to be held back until the speculation can be proved right, and have to be withdrawn in case the speculation was wrong. In contrast to related work, our approach has been implemented purely in software using standard hardware to address a broad field of multicore processors. Moreover, a software implementation allows us to dynamically adapt parameters to the needs of the application. This allows us to enforce a user-defined hit ratio of speculation that might even switch speculation off. After a detailed description of this approach and a discussion of possibilities of its implementation, we show its feasibility using a couple of benchmarks. In these benchmarks, the use of speculation achieved an average speedup of 1.2 compared to the non-speculative out-of-order execution.

Schedule-Extended Synchronous Dataflow Graphs

Synchronous dataflow graphs (SDFGs) are used extensively to model streaming applications. An SDFG can be extended with scheduling decisions, allowing SDFG analysis to obtain properties, such as throughput or buffer sizes for the scheduled graphs. Analysis times depend strongly on the size of the SDFG. SDFGs can be statically scheduled using static-order schedules. The only generally applicable technique to model a static-order schedule in an SDFG is to convert it to a homogeneous SDFG (HSDFG). This may lead to an exponential increase in the size of the graph and to suboptimal analysis results (e.g., for buffer sizes in multiprocessors). We present techniques to model two types of static-order schedules, i.e., periodic schedules and periodic single appearance schedules, directly in an SDFG. Experiments show that both techniques produce more compact graphs compared to the technique that relies on a conversion to an HSDFG. This results in reduced analysis times for performance properties and tighter resource requirements.