Data Intensive Computing: From Modeling to Implementation

Abstract

Data intensive computing encompasses applications that mostly perform data processing in regular patterns. Traditionally, such applications have been found, e.g., in image processing, audio processing, telecommunications and radar signal processing. With the immense growth of the mobile consumer electronics market, data intensive computing is present in billions of devices. In contrast to general-purpose computing, the regularity of data intensive computing enables intelligent design choices to be made in specification, modeling, design space exploration, software design, compilation and hardware design. However, unlike classic signal processing, contemporary data intensive applications, such as a H.265 video decoding or cognitive radio radio systems cannot be described with fully static representations. This dynamic nature of contemporary data intensive applications has its implications to all layers of system design, from higher-level software to hardware implementation. This special issue covers topics from the whole spectrum of design aspects for data intensive computing. Included are three articles that address dataflow specification and analysis of applications, four articles that address programmable processing hardware for data intensive applications and one publication that deals with both software and hardware design aspects. Article Parameterized Sets of Dataflow Modes and Their Application to Implementation of Cognitive Radio Systems (doi:10.1007/s11265-014-0938-4) presents a novel dataflow modeling technique named parameterized sets of modes (PSM) that addresses the important issue of modeling reconfigurable data intensive systems. After presenting a formal definition of the new concept, a cognitive radio application example is presented. Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs (doi:10.1007/ s11265-014-0952-6) is an article that concentrates on the memory usage analysis and optimization of applications that target MPSoC platforms. The application is modeled with the well-known Synchronous Dataflow formalism, based on which the memory usage analysis and optimization is performed. Experiments are performed with several data intensive applications on Intel and Texas Instruments DSP multicores. The paperModeling Resolution of Resources Contention in Synchronous Data Flow Graphs (doi:10.1007/s11265-0140923-y) addresses interprocessor communication contention on multicore platforms. The proposed approach uses Synchronous Dataflow graphs to model applications and to perform the resource contention analysis. Experiments consist from random application graphs to well-known data intensive applications, such as video and audio codecs. When going towards the hardware implementation level, issues such as processor instruction-set architectures suitable for data intensive computing become of interest. To this end, Code Density and Energy Efficiency of Exposed Datapath Architectures (doi:10.1007/s11265-014-0924-x) gives an overview of an instruction-set design direction where nontraditional aspects of the datapath are exposed to the control of the programmer in order to improve energy efficiency and instruction-level parallelism. The article looks at several proposed variations of the so called exposed datapath architectures with focus on their instruction word width overheads. A Low Energy Wide SIMD Architecture with Explicit Datapath (doi:10.1007/s11265-014-0950-8) proposes a dataoriented processor architecture which exposes the bypass P. Jaaskelainen (*) Tampere University of Technology, Tampere, Finland e-mail: pekka.jaaskelainen@tut.fi