Output Switching Research Articles

Retracted] Research on Recognition Method of Basketball Goals Based on Image Analysis of Computer Vision

Moving target detection is involved in many engineering applications, but basketball has some difficulties because of the time‐varying speed and uncertain path. The purpose of this paper is to use computer vision image analysis to identify the path and speed of a basketball goal, so as to meet the needs of recognition and achieve trajectory prediction. This research mainly discusses the basketball goal recognition method based on computer vision. In the research process, Kalman filter is used to improve the KCF tracking algorithm to track the basketball path. The algorithm of this research is based on MATLAB, so it can avoid the mixed programming of MATLAB and other languages and reduce the difficulty of interface design software. In the aspect of data acquisition, the extended EPROM is used to store user programs, and parallel interface chips (such as 8255A) can be configured in the system to output switch control signals and display and print operations. The automatic basketball bowling counter based on 8031 microprocessor is used as the host computer. After the level conversion by MAX232, it is connected with the RS232C serial port of PC, and the collected data is sent to the workstation recording the results. In order to consider the convenience of user operation, the GUI design of MATLAB is used to facilitate the exchange of information between users and computers so that users can see the competition results intuitively. The processing frame rate of the tested video image can reach 60 frames/second, more than 25 frames/second, which meet the real‐time requirements of the system. The results show that the basketball goal recognition method used in this study has strong anti‐interference ability and stable performance.

A 10-Output, Single-Inductor-Multiple-Output DC–DC Buck Converter With Integrated Output Capacitors for a Sub-mW System-on-Chip

Emerging sub-mW near-threshold-voltage system-on-chips require new power management architecture that can create multiple voltage domains with the fewest possible off-chip passives. To fulfill this need, we propose an ultra-low-power single-inductor–multiple-output dc–dc buck converter in a 65-nm CMOS process. Featuring a comparator-based output switch controller and a digital pulse-width modulation controller for ultra-low feedback latency, this dc–dc converter takes 1-V input voltage and produces ten independent output voltages from 0.4 to 0.8 V at the aggregated power delivery of 0.583 mW. It has ten 200-pF on-chip output capacitors and one 82- $\mu \text{H}$ off-chip inductor and achieves the peak power conversion efficiency of 83.4%.

CBPWM and SVPWM equivalent relationship on single‐phase NPC N ‐level inverters with arbitrary sequence

Single-phase multilevel neutral-point-clamped (NPC) voltage source inverter has been widely applied in AC traction drive system, the carrier-based pulse width modulation (CBPWM) method and the space vector pulse width modulation (SVPWM) method are mainly two modulation methods for single-phase NPC multilevel converters, and there is a certain relationship between these two modulation strategies. In this study, the unified relationship between SVPWM and CBPWM in single-phase three-level and five-level NPC has been analysed. Then by injecting the zero-sequence component into the initial modulation wave, the same switching state and output current as SVPWM can be achieved through modulation waves decomposed under the CBPWM strategy. Finally, the unified theory of SVPWM and CBPWM in an N-level inverter with an arbitrary number of segments sequence was deduced. The simulation and experimental results illustrate that the unified theory between CBPWM and SVPWM is correct. With the zero-sequence injected, CBPWM can realise the same effect as SVPWM, but the former is simpler than the latter, which is easy to promote for higher-level applications.

Research on Improved D-NPC Three Phase Three Level Converter and Its Control Strategy

Diode Neutral Point Clamped (D-NPC) three-level topology with simple structure and low withstand voltage of single power device is suitable for medium voltage applications. Due to the long working time and high temperature of the inner tube in the main bridge arm of the d-npc structure, the design of the radiator is difficult, and the output current and switching frequency are limited. In order to solve this problem, this paper proposes an improved d-npc three-phase three-level topology, optimizes the traditional seven segment SVPWM modulation strategy, builds a simulation model based on PMSM control device, and proves the correctness and feasibility of the improved structure.

Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology

In this brief, different characteristics of current starved ring oscillator (CSRO) circuits are investigated and four new designs are proposed. A new parameter, known as phase noise bandwidth product (PNBP), is also proposed to address the trade-off between phase noise performance and frequency tuning range while designing ring oscillators (ROs). The proposed circuits are compared with existing architectures in terms of power consumption, frequency bandwidth, maximum frequency, phase noise, power delay product (PDP) and PNBP. For performance evaluation, three-stage CSROs have been implemented in Cadence software using the 16 nm PTM High Performance (HP) technology model. Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement. Moreover, all four proposed architectures show improved performance in terms of PDP and PNBP compared to conventional CSRO. The performance of the CSROs is also observed and compared with respect to the variations in process-voltage-temperature (PVT) parameters.

Calculation of Semiconductor Power Losses of a Three-Phase Quasi-Z-Source Inverter

This paper presents two novel algorithms for the calculation of semiconductor losses of a three-phase quasi-Z-source inverter (qZSI). The conduction and switching losses are calculated based on the output current-voltage characteristics and switching characteristics, respectively, which are provided by the semiconductor device manufacturer. The considered inverter has been operated in a stand-alone operation mode, whereby the sinusoidal pulse width modulation (SPWM) with injected 3rd harmonic has been implemented. The proposed algorithms calculate the losses of the insulated gate bipolar transistors (IGBTs) and the free-wheeling diodes in the inverter bridge, as well as the losses of the impedance network diode. The first considered algorithm requires the mean value of the inverter input voltage, the mean value of the impedance network inductor current, the peak value of the phase current, the modulation index, the duty cycle, and the phase angle between the fundamental output phase current and voltage. Its implementation is feasible only for the Z-source-related topologies with the SPWM. The second considered algorithm requires the instantaneous values of the inverter input voltage, the impedance network diode current, the impedance network inductor current, the phase current, and the duty cycle. However, it does not impose any limitations regarding the inverter topology or switching modulation strategy. The semiconductor losses calculated by the proposed algorithms were compared with the experimentally determined losses. Based on the comparison, the correction factor for the IGBT switching energies was determined so the errors of both the algorithms were reduced to less than 12%.

An 8-Bit Digitally Operated Micromachined Accelerometer

This work presents successful implementation and characterization of an 8-bit digitally operated micromachined accelerometer. Such device is comprised of an electrostatically tunable acceleration switch with 8 sets of electrostatic tuning electrodes. Similar to bits in a binary number, the tuning force of each electrode set increases by a factor of 2 with respect to the adjacent electrode set. A fabricated device has been interfaced with a micro-controller performing a binary search by controlling state of different tuning electrodes (ON or OFF) to interpret the acceleration with 8 bits of resolution. Measurement results show good agreement between the applied acceleration and the binary acceleration output of the sensor reported by the controller. The tested 8-bit prototype has full-scale acceleration of 2.7g with resolution 10.5 mg s (1/28 of full scale). Requiring only a bias voltage for operation (zero static current) and readout of the switch output (a digital high or low voltage) that can be performed directly by a digital controller, such devices can lead to ultra-low power accelerometers by eliminating the need for an analog-front-end. [2020-0201]

Phase characteristics of E class amplifier with various output networks

Phase shift of E class amplifiers with classical output network and output network that satisfies E class loading impedance conditions twice in the frequency band were studied by simulation and experimentally. The phase shift across switch in nominal operation mode was investigated analytically. The phase shift across switch in suboptimal class E operation mode that occurs while altering the operation frequency was investigated as well. The simulation method was the harmonic balance analysis using the switch model that considers the structure of power MOSFET device, namely, the existence of antiparallel diode pair that alters the switch current waveform. The input and transition capacitances of the transistor were considered. Experimental measurement of the phase shift was performed utilizing the recorded digitized waveforms of the switch input and output voltages by computing the phases of the voltages’ first harmonics with the help of Fast Fourier Transform. It was observed that characteristics of phase shift at switch output and amplifier output are dependent on the kind of load network. The relationship between the phase shift at the switch and hodograph of the loading impedance was demonstrated. For the network with double fulfilment of class E conditions that has a loop in the loading impedance hodograph the switch phase shift dependency has an extremum, which provides an opportunity to obtain the same phase shift at two frequencies within the operating frequency band. That facilitates control of the phase-frequency characteristic and the group delay of the amplifier. Knowledge of the phase-frequency dependency simplifies the conditions for calculation of the phase shift in the feedback network. The obtained results are useful for design of class E oscillator operating in a wide frequency band.

Passively Q-switched multiple visible wavelengths switchable YVO4 Raman laser

The output characteristics of orange-yellow-green emission switchable output generated in a compact passively Q-switched YVO4 Raman laser were investigated for the first time. A Cr4+:YAG/YAG composite crystal was adopted as the saturable absorber to realize passively Q-switch operation. The diode-end-pumped Nd:YAP laser operating at 1.08 μm was used to drive an a-cut YVO4 crystal for realizing the first-Stokes wavelength at 1.2 μm. Selective frequency mixing of the first-Stokes and the fundamental waves in a shared cavity were achieved by an angle-tuned BBO crystal. Under an incident pump power of 12.05 W, the average maximum output powers of 472 mW for 597.4 nm orange light, 431 mW for 567.2 nm yellow light and 803 mW for 539.9 nm green light could be switchable output with respective pulse widths of about 2.6, 2.4 and 37.6 ns. Under the maximum incident pump power, the pulse repetition frequency and the single pulse energy were approximately 11.6, 10.9, 13.4 kHz and 40.7, 39.5, 59.9 μJ, respectively.

SiC-MOSFET and Si-IGBT-Based dc-dc Interleaved Converters for EV Chargers: Approach for Efficiency Comparison with Minimum Switching Losses Based on Complete Parasitic Modeling

Widespread dissemination of electric mobility is highly dependent on the power converters, storage systems and renewable energy sources. The efficiency and reliability, combined with the emerging and innovative technologies, are crucial when speaking of power converters. In this paper the interleaved dc–dc topology has been considered for EV charging, due to its improved reliability. The efficiency comparison of the SiC-MOSFET and Si-IGBT-based converters has been done on wide range of switching frequency and output inductances. The interleaved converters were considered with the optimal switching parameters resulting from the analysis done on a detailed parasitic circuit model, ensuring minimum losses and maintaining the safe operating area. The analysis included the comparison of different inductors, and for the selected ones the complete system efficiency and cost were conducted. The results indicate the benefits when SiC-MOSFETs are applied to the interleaved dc–dc topology for wide ranges of output inductances and switching frequencies, and most importantly, they offer lower total volume but also total cost. The realistic and dynamic models of power devices obtained from the manufacturer’s experimental tests have been considered in both LTspice and PLECS simulation tools.

Design of a Kind of Low-Cost and High-Precision Power Measuring Device

A kind of low-cost and high-precision power measuring device is designed, which is realized by hardware circuit and embedded software. The signal acquisition circuit, switching value input and output circuit, communication circuit of the device are analyzed. The power calculation program, storage program, timer interrupt program and communication program are described. The device has been applied in the field, and the application shows that the device meets the requirements of industrial level and has the merits of low cost, high precision and high stability.

Hybrid Renewable Energy Based CFSI for and Motor Application using ANFIS Based MPPT and IFOC Controller

In many industrial applications, the varying speed of the motor drives has become essential for the fast dynamic load conditions. Therefore, the detailed analysis of Field Oriented Control (FOC) with the sensor-less technique of BLDC is proposed where the reference speed is obtained from the MPPT based ANFIS controllers for control the speed. The FOC not only control the magnitude but also provides the phasor control. With Back-EMF estimation process, the motor is applied to obtain the torque ripple minimization and correct speed control using simpler IFOC. It is used to estimate speed in a sensorless and to map the continuous velocity variation. This approximate velocity is used to activate and to predict hall switching output less BLDC motor signals with low tension MATLAB / Simulink tool is using for results verification.

Three-Level Discontinuous PWM for Loss and Thermal Redistribution of T-NPC Inverter at Low Modulation Index

With conventional pulsewidth modulation (PWM) strategies, the switches of a three-level T-type neutral-point-clamped (T-NPC) inverter are not equally utilized at modulation indices lower than 0.5, limiting the inverter power throughput. The inner switches incur more losses than the outer switches. This article investigates a series of space-vector-based discontinuous PWM (DPWM) templates for modulation indices lower than 0.5. The templates relocate the phase current from the inner to the outer switches of a T-NPC inverter. Using them, the device losses are reduced and get redistributed more equally among the inner and outer switches, enabling a higher inverter output current or switching frequency. Confirmatory simulation and experimental results are provided to demonstrate the potential of the three-level DPWM templates in comparison to the conventional PWM templates.

Complete ZVS Analysis in Dual Active Bridge

Zero-voltage-switching (ZVS) has been widely applied in widebandgap devices based on high-switching-frequency converters, for instance, dual-active-bridge isolated dc-dc converter, which consists of two H-bridges. To secure ZVS for all eight switches, previous literature mostly focuses on half-bridge to analyze switching transitions, which, however, is rather incomplete due to ignoring the impact of modulation strategies and cannot fulfill all circumstances. In this letter, the whole H-bridge is used as a unit to analyze the ZVS transient process, addressing the ZVS setting in different modulation strategies. The minimal initial inductor energy to complete the ZVS process is also quantified, which in return can reduce the transformer current, thereby enhancing the efficiency. Furthermore, the accurate ZVS transition time is derived incorporating with the nonlinearity of switch output capacitance, which can be further used to set the dead-band time. An H-bridge prototype with SiC devices is built up to verify the theory proposed in this letter.

AC–DC boost converter based on T-type multi-state switching cell and output voltage balancing

A novel topology of the ac–dc power converter to supply neutral-point-clamped inverters used in ac motor drives and wind offshore power grids is proposed. It is based on the T-type multi-state switching cell, which allows obtaining a five-level voltage waveform downstream of the input filter inductor. The converter presents a high voltage gain due to the transformer secondary windings associated with series-connected diode rectifiers. Prominent main characteristics of this topology include power factor correction, operation of the filter inductor at twice the switching frequency, reduced conduction losses in the semiconductors, and voltage balance across the output capacitors. To verify the operating principle of the converter a design example is described, considering that the converter specifications are: output power of 3 kW; rms input voltage of 110 V; total output voltage of 1 kV, which is equally divided among four capacitors and switching frequency of 20 kHz. Simulation results are shown to validate the theoretical assumptions and verify the behaviour of the rectifier in terms of dynamic response while also supplying unbalanced loads.

Observer-based finite-time output feedback control of heat equation with Neumann boundary condition

This paper is concerned with the problem of boundary observer-based finite-time output feedback control for a heat system with Neumann boundary condition and Dirichlet boundary actuator. In this system, it is endowed a single sensor at the left boundary and actuator at the right boundary. First, a backstepping finite-time observer is designed. Based on linear switching observer gains with state-dependent switching, the proposed observer estimates the system state variables in a finite-time only using one displacement boundary measurement. Then, an observer-based linear switching output feedback control with state-dependent switching is presented, which steers any solution of the output feedback closed-loop system to zero in a finite-time. Finally, the simulation results are provided to support the theoretical results.

Design of an 8‐bit time‐mode cyclic ADC based on macro modeling

SummaryThis work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated.

Multi-Orthogonal High-Order Mode Converter Based on Acoustically Induced Fiber Gratings

We experimentally investigate the generation of high-order modes (HOMs) with flexible switchable output. Cascaded acoustically induced fiber gratings (AIFGs) act as mode converters. A periodic micro-bending in the AIFG is produced by travelling flexural acoustic wave, and two modes with adjacent azimuthal numbers can be coupled to each other. Different HOMs (LP21a/b and LP11a/b) could be obtained just by tuning the frequency of the radio frequency (RF) driving signal. The dependence of RF frequencies on the two acousto-optic (AO) coupling stages is theoretically analyzed and experimentally verified. Based on cascaded AIFGs mode converter, a multiple-level intensity modulator and an all-fiber Yb-doped laser with flexible mode switching output of HOMs (LP21a/b and LP11a/b) are demonstrated. Moreover, by optimizing the outer diameter of the second part of the AO coupling regions, the mode conversion between LP01 and LP21 can be realized by applying a single frequency on the piezoelectric transducer (PZT).

A Wide Tunable Hysteresis CML Delay Cell for High Frequency

In this letter, a novel high-speed widely tunable voltage-controlled current mode logic (CML) delay cell is implemented in a 65-nm CMOS technology. Variation in the delay of the proposed delay cell is based on the hysteresis control of the output switching threshold by altering the tail current of the CML buffer. The simulation for a single stage cell shows a delay variation of at least 11% in the input clock period at 12.5-GHz clock frequency. While in measurement, the delay line with three stages of the proposed cells shows more than a 38-ps delay variation with an output rms jitter of 1.67 ps for the 9.82-GHz input clock frequency. At this frequency with the highest delay variation, along with additional buffers and delay controllers, the delay line consumes 7.6 mW of power with 1.2-V core supply. The delay line consumes the silicon area of 0.0285 mm2 in the 65-nm technology node.

The Single Bit Request Grant (SBRG) Scheduling Algorithm for Input-Queued ATM Switches

In this paper, we propose an efficient single-iteration single-bit request scheduling algorithm for input-queued ATM switches that based on a new arbitration technique called the Single Bit Request Grant (SBRG) algorithm. The operation of the SBRG depends on the concept known as “the preferred input-output pairs first”, and the arbitration requests starts from switch output ports to reduce the number of issued request signals. Compared to other single-iteration algorithms, simulation results show that the SBRG maximizes the match size and improves the switch delay/throughput performance, especially when the load increases. Also, the proposed algorithm reduces the complexity of some of the existing algorithms by decreasing the number of input-output transferred messages, and by the absence of any encoding/decoding mechanism that can be used in some existing algorithmsto reduce the size of request signals to one bit.