Switch Chip Research Articles

Design of SEE-Tolerant analog switch chip with a novel diode structure *

This paper proposes a novel circuit-level design in order to enhance the radiation tolerance of an analog switch integrated circuit. After analyzing the mechanisms of single-particle sensitivity in a high-voltage analog switch chip fabricated using a commercial 1 μm complementary metal–oxide–semiconductor process, a diode unit was employed to reduce the V GS (voltage between the gate and the base) of the parasitic triode within the metal–oxide–semiconductor field-effect transistor of the switch. This reduction lowered the probability of activating the parasitic triode in response to single-event effect (SEE). Subsequently, single-particle irradiation experiments proceeded with the high-voltage analog switch chip, both with and without the diode unit. In the unreinforced device, the current of the power supply reached 100 mA within 11 s of single-particle irradiation at 75.8 MeV•cm2 mg−1. In contrast, in the reinforced device, the current of the power supply remained relatively stable under irradiation at both 37.2 and 75.8 MeV•cm2 mg−1. These findings indicate that the reinforced analog switch chip exhibits an SEE tolerance exceeding 75.8 MeV•cm2 mg−1, highlighting its potential to enhance the radiation tolerance of analog switches.

Optical switching will innovate intra data center networks [Invited Tutorial

Reflecting the recent slow-down in Moore’s law and the proliferation of artificial intelligence/machine learning workloads, the performance and energy consumption of networks are becoming barriers in high-performance computing (HPC) and data centers. Optical switches are expected to break these barriers, and indeed their introduction has recently commenced in data centers. This paper discusses how optical switching technologies can innovate future intra data center networks. Hyperscale data centers are much bigger in scale, and network requirements are slightly different from those of HPC. This paper focus on data center networks, since the impact of optical technologies will be more significant in data centers than in HPC. In addition to the scale issue, important metrics to be considered for network design are traffic characteristics and latency, both of which are highlighted in this paper. For hybrid (electrical packet and optical circuit) switching networks, the target latency for the optical circuit switch network (connection setup/teardown time) is shown to be around 10 µs, and the needed technologies are clarified and verified by experiments. The optical switch can simplify the present multi-tier switching network above tier-1 switches into a single tier configuration, which is possible with the development of efficient large port count optical switches. Among the different switching architectures, combining the different dimensions of space and wavelength is shown to be one of the best solutions. Fast switching needs fast device response time. Si photonics devices using Mach–Zehnder interferometers or ring-resonator-based switches and tunable filters are the most promising candidates; they offer cost-effective mass-production and fast operation and so are excellent candidates for the optical switches envisaged. Another critical technology to maximize the benefits of optical switches is a simple and low-latency control mechanism. Different approaches have been suggested as summarized in this work. Among them, harnessing optical switch parallelism is a unique technique that matches recent advances in electrical switch chips. A fast control network is realized by using a fully decentralized and asynchronous control mechanism. A hyperscale data center offers a wide variety of services, and no one system fits all needs. Optimization of parameters is an important task for maximizing the impact of optical switching in different kinds of data centers.

Silicon based integrated photonic chip technology for datacenter optical interconnection

With the rise of the modern Internet of Things, big data and other industries, the human society’s demand for information increases rapidly, and the demand for broadband network capacity shows a dramatic growth trend. As its core support, optical communication system and data center are facing major challenges. With the characteristics of small volume, light weight and low power consumption, optoelectronic integrated devices are the key devices to break through the bottleneck of optical communication system and data center optical interconnection. In this paper, silicon-based integrated optical switching technology and multiplexing technology applied for datacenter optical interconnection are studied. The implementation methods and technical bottlenecks of silicon-based integrated optical switching chips and mode multiplexing/demultipelxing chips are discussed. Moreover, the future of silicon-based integrated photonic technology is prospected.

Design of Clock Synchronization of Base Station by Using 8A34002

The stability of the entire base station depends on the synchronization of the base station’s clock. The clock synchronization management chip 8A34002 supports SyncE Ethernet and IEEE 1588. In this architecture, the GPS receiver, SSI, and master/slave switching device all emit PPS/TOD signals. PPS/TOD signals are input into the FPGA, which outputs one PPS/TOD signal. The PPS/TOD signal enters 8A34002 in this design scheme, and the DPLL of 8A34002 provides filtering and clock-following output. The 8A34002‘s signal output is used as the system’s clock after processing. The switching chip, X86 main control chip, and BBU base station board are all driven by the system clock, which serves as a reference clock. The 8A34002 uses four DPLLs, one each for the SyncE, PTP, GNSS, and test functions.

Broadband 32 × 32 Strictly‐Nonblocking Optical Switch on a Multi‐Layer Si3N4‐on‐SOI Platform

AbstractLarge‐scale silicon optical switches are essential to support the ever‐increasing data traffic. Among the various switching architectures, the well‐known switch‐and‐select (S&S) architecture has the advantages of low crosstalk and strict non‐blocking. However, it suffers from high path‐dependent losses as the waveguide crossings increase dramatically with the number of ports. In this paper, a large‐scale 32 × 32 S&S optical switch on a multi‐layer Si3N4‐on‐SOI platform is reported. The optical switch chip incorporates 1984 broadband thermo‐optic Mach‐Zehnder interferometer (MZI)‐based switch elements, 246 016 three‐dimensional (3D) waveguide crossings, and 2048 interlayer couplers. Both ≈1‐mdB‐loss 3D waveguide crossings and ≈0.3‐dB‐loss interlayer couplers are realized, significantly reducing the overall insertion loss and footprint of the switch chip. The measured average fiber‐to‐fiber insertion loss is 12.88 dB at the 1580 nm wavelength. In addition, the crosstalk is less than −20.7 dB over the 110‐nm wavelength range. The power consumption of the entire switch chip is only ≈0.98 W due to the air trenches and substrate undercut. High‐fidelity optical transmission of a 50 Gb s−1 quadrature phase‐shift keying signal verifies the high‐performance routing capability of this chip. These results indicate that the large‐scale optical switch with broadband, low crosstalk, and high‐power efficiency is promising for datacenter optical network applications.

A Long‐Range and Nearly Passive RFID‐Controlled Information Metasurface

AbstractInformation metasurfaces (IMSs) have been considered to be a revolutionary technology for improving the spectral efficiency of sixth‐generation (6G) wireless communications due to their superior ability to manipulate electromagnetic (EM) waves. However, there are still problems to be solved before the widespread application of IMSs. The first is to reduce power consumption, and the second is to achieve a long‐range remote control. In this paper, a long‐range and nearly passive radio frequency identification (RFID)‐controlled IMS is proposed. The proposed IMS comprises four RFID tags and 8 × 8 elements, each of which is integrated with a single‐pole‐double‐throw switch chip to achieve 1‐bit phase reconfigurability. With the remote control of the RFID system, the IMS can be programmed to switch between three functionalities, including beam splitting, beamforming, and EM‐wave absorption. Experiments are performed and the beam‐splitting functionality is demonstrated. The measurement results indicate that the wireless communication between the RFID reader and the IMS is robust within 21.7 m. Additionally, the power consumption of the IMS is as low as 0.576 mW, which can be negligible. The scheme presented in this paper paves the way for the large‐scale applications of IMSs in 6G wireless communications.

High frequency application of ultrafine submicron FeBP amorphous soft magnetic composites

A novel amorphous soft magnetic composites (ASMCs) for hundreds MHz frequency applications have been prepared under the hot-pressing molding by ultrafine submicron FeBP amorphous powders. These ultrafine submicron FeBP amorphous particles were synthesized with the NaBH4 chemical reduction method and the particles size was regulated by the drop rate of the reducing agent. The morphology, microstructure, elemental composition and high-frequency magnetic properties of the amorphous soft magnetic composites was systematically investigated. The particle sizes of FeBP amorphous powders are distributed in 600–900 nm which gradually increase with the decrease of the drop rate of the NaBH4 aqueous solution. Meanwhile, the Fe element content and saturation magnetization strength of the amorphous powder increase and the coercivity gradually decreases. The corresponded ASMCs also appear a commensurate permeability in the range of 6–9 responding to the GHz high frequency range with the lowest loss tangent only 0.20 and 0.44 at 500 MHZ and 1 GHz, respectively. Such ultrafine amorphous soft magnetic composites have enormous potential for high frequency applications in wide band gap semiconductor switching power supplies, RF inductors and chips.

Surface H‐field mapping of a GaAs single pole double throw switch chip based on quantum diamond probe

With the improvement of design capability and manufacture technology, the integration as well as the complexity of chips have also increased dramatically, and it becomes critical to realize noninvasive electromagnetic inspection of chips at higher resolutions. In this paper, we propose a submicron-resolution microwave near-field imaging system based on the nitrogen-vacancy center (NV) in diamond, which mainly consists of an optical hardware system and a software control system, and can be used for nondestructive imaging of microwave fields on the surface of integrated circuits with submicron resolution. We applied this technique to scan the surface microwave field distribution of a GaAs single pole double throw switch chip. The scanning imaging system can image the near-field magnetic distribution for the chip, which provides a new solution for analyzing the current distribution on the chip surface and thus addressing problems such as excessive current or crosstalk. It is worth mentioning that the diamond NV color center-based sensor has a very high-spatial resolution and magnetic field detection sensitivity at room temperature, while the dielectric constant of natural diamond is 5.5, which also provides the possibility of diamond as a sensor in complex radiation environments and is an ideal detector material for near-field imaging of electromagnetic fields.

Algorithmic TCAMs: Implementing Packet Classification Algorithms in Hardware

The adoption of cloud computing and the deployment of new services require more and more computing and networking resources in large data centers. In particular, there is a need for faster, rich featured switches. Today, switching integrated circuits can handle more than 50 Tb/s and are expected to reach 100 Tb/s next year. This trend is likely to continue, approaching petabit capacities in a few years. At the same time, switches need to support more advanced packet classification features. This poses many challenges to the designers of switching integrated circuits, creating a need for innovations to move forward. One of those challenges is to support programmable packet classification with large rulesets at wire speed using limited silicon footprint. Unfortunately, traditional solutions like ternary content addressable memories (TCAMs) have high cost in area and power, and therefore are not a viable option for large on-chip rulesets, so new alternatives are needed. In the last two decades, researchers have extensively studied the problem of packet classification, proposing many algorithms based on standard memories, mostly targeting software implementations. These packet classification algorithms could be a solution to enable large on-chip classification rulesets using standard memories. However, porting the standard packet classification algorithms to a hardware implementation is not a trivial task, due to the different requirements and the different kinds of memory and computing resources available on application-specific integrated circuit (ASIC) switching chips. This article describes a packet classification design tailored for high-speed switching integrated circuits, which is currently used in the NVIDIA® Mellanox® Spectrum® switching ASIC product line, illustrating how to solve the mismatch between the usual software-based classification algorithms and the specific requirements of a hardware implementation.

Design of 30 V High-Voltage Low-Power Radiation-Tolerant Analog Switch IC

In this study, a circuit- and device-level design was developed to improve the radiation tolerance of an analog switch integrated circuit (IC), which was fabricated using a commercial 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> bipolar–CMOS–DMOS (BCD) process. Both circuit- and layout-level approaches were used to improve the total ionizing dose (TID) tolerance of the IC. In the circuit-level approach, a level shift unit was used to reduce the amount of oxide traps. Under the layout-level approach, a ring gate and a doping ring were added to reduce the leakage current. Moreover, the optimum doping concentration of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {WELL}}$ </tex-math></inline-formula> and length of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N_{+}$ </tex-math></inline-formula> drift zone were calculated for the n-MOSFET based on simulations to obtain the best device structure and improve the single-event burnout (SEB) tolerance. The radiation tolerance was tested experimentally. The results indicated that the newly designed 30-V high-voltage low-power analog switch chip had a TID tolerance >300 krad(Si) and a SEB tolerance >75 MeV cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, which are useful to improve the radiation-tolerant capability of high-voltage analog switches.

Preventing hardware Trojans in switch chip based on payload decoupling

Hardware Trojans in integrated circuit chips have the characteristics of being covert, destructive, and difficult to protect, which have seriously endangered the security of the chips themselves and the information systems to which they belong. Existing solutions generally rely on passive detection techniques. In this paper, a hardware Trojans active defense mechanism is designed for network switching chips based on the principle of encryption algorithm. By encoding the data entering the chip, the argot hidden in the data cannot trigger the hardware Trojans that may exist in the chip, so that the chip can work normally even if it is implanted with a hardware Trojans. The proposed method is proved to be effective in preventing hardware Trojans with different trigger characteristics by simulation tests and practical tests on our secure switching chip.

A 28-GHz Switched-Beam Antenna with Integrated Butler Matrix and Switch for 5G Applications.

This work presents a 28-GHz Butler matrix based switched-beam antenna for fifth-generation (5G) wireless applications. It integrates a 1 × 4 microstrip antenna, a 4 × 4 Butler matrix, and a single-pole four-throw (SP4T) absorptive switch in a single planar printed circuit board and is housed in a metal enclosure. Co-integration of a packaged switch chip with the Butler matrix based switched-beam antenna greatly enhances the form factor and integration level of the entire system. A wideband two-section branch line coupler is employed to minimize the phase and magnitude errors and variations of the Butler matrix. The aluminum metal enclosure stabilizes the electrical performances, reduces the sidelobes, and improves the structural stability. The fabricated antenna with the metal enclosure assembled has a dimension of 37 × 50 × 6.2 mm3. With an RF input signal fed to the antenna’s input port through a single Ka-band connector, and the switching states chosen by 2-bit dc control voltages, the antenna successfully demonstrates four directional switched beams. The beam switching operations are verified through the over-the-air far-field measurements. The measured results show that the four beam steering directions are −43°, −17°, +10°, +34° with side lobe levels < −5.3 dB at 28 GHz. The antenna also shows reasonably wideband radiation patterns over 27–29 GHz band. The 10-dB impedance bandwidth is 25.4–27.6 GHz, while a slightly relaxed 8-dB bandwidth is 25.2–29.6 GHz. Compared to previous works, this four-directional switched-beam antenna successfully exhibits the advantages of high integration level and satisfactory performances for the 28-GHz 5G wireless applications.

Strictly Non-Blocking 8 × 8 Silicon Photonics Switch Operating in the O-Band

In this article, we report the development of a strictly non-blocking 8 × 8 silicon photonics switch designed to operate in the O-band. This 8 × 8 switch is based on path-independent insertion-loss topology and is composed of 2 × 2 thermo-optic double Mach-Zehnder switches and adiabatic intersections. The fabricated 8 × 8 switch chip is electrically packaged with a ceramic chip carrier and inserted into a socket on a printed circuit board. As for the optical connection, an optical fiber array and edge couplers are used. The fabricated 8 × 8 switch exhibits an average fiber-to-fiber insertion loss of 16.6 dB, including a fiber to chip coupling loss of 11.2 dB and crosstalk of less than -30 dB over a bandwidth of 70 nm. Moreover, we investigate the nonlinear characteristics of Si devices in the O-band. The cw input/output response and degradation free 28-Gb/s OOK signal transmission demonstrate that two-photon absorption and four-wave mixing are not significant when the input power is less than approximately 4 mW. These results indicate that it is possible to produce low-loss and low-crosstalk silicon photonics switches that operate in the O-band.

On-Chip Multi-Dimensional 1 × 4 Selective Switch With Simultaneous Mode-/Polarization-/Wavelength-Division Multiplexing

Optical selective switch based on silicon photonics offers the advantages of compactness, low power consumption and flexible data management in future optical communication networks. Multi-dimensional (mode, polarization, wavelength) multiplexing transmission has become increasingly important for capacity scaling, while the multi-dimensional selective switch is still full of challenges, especially the integrated solution. Here, we propose and demonstrate on-chip multi-dimensional $1\times \text{N}$ selective switch with simultaneous mode-, polarization- and wavelength-division multiplexing. The monolithic integration on a single silicon chip consists of building blocks of cascaded asymmetrical directional couplers for mode/polarization (de)multiplexing, cascaded microring resonators for wavelength (de)multiplexing, and cascaded thermal-tuning Mach-Zehnder interferometers for selective switching. A multi-dimensional $1\times 4$ selective switch chip on silicon platform is fabricated for proof-of-concept demonstration of simultaneous mode, polarization and wavelength selective switching. The inter-mode/inter-polarization crosstalk and intra-mode/inter-port crosstalk are characterized in the experiment, showing favorable performance with worst crosstalk values of −15.6 and −25.38 dB, respectively. The demonstrations may open up new perspectives for on-chip solutions to multi-dimensional optical signal processing for superior capacity scalable optical communication systems.

The Reliability Design of Switch Chip Based on THENA Process Stimulation System

This paper mainly focuses on the 2CK6642 silicon switch diode chip, which is mainly used for the surface-mounted packaging device of CLCC-3 metal ceramic. Different from that of ordinary diode, the internal structure of 2CK6642 silicon switch diode has a high resistance region I in the middle of Type P and Type N silicon materials, forming a P-I-N structure. Silvaco TCAD interactive tools, i.e. ATHENA process stimulation system and ATLAS device stimulation system, are used to conduct the design and stimulation of 2CK6642 silicon switch diode chip, so that alternative plugging with external devices could be achieved finally.

Bottom-metal-printed thermo-optic waveguide switches based on low-loss fluorinated polycarbonate materials.

In this work, thermo-optic (TO) waveguide switches are designed and fabricated based on the bottom-metal-printed technique. Low-loss fluorinated polycarbonate (AF-Z-PC MA) and polymethyl methacrylate (PMMA) are used as core and cladding materials, respectively. The thermal stability and optical absorption characteristics of AF-Z-PC MA are analyzed. The optical and thermal field distributions of the TO switch are simulated. The insertion loss and extinction ratio of the device are found to be 4.5 dB and 19.8 dB, respectively, at a wavelength of 1550 nm. The on-off time of the switching chip is 80 µs. The electrical power consumption is approximately 8.8 mW. The proposed low-loss fluorinated polymer TO waveguide switch realized by bottom-metal-printed fabrication technology is suitable for large-scale integrated photonic circuit systems.

Frequency-Adjustable Planar Folded Slot Antenna Using Fully Integrated Multithrow Function for 5G Mobile Devices at Millimeter-Wave Spectrum

This article describes a low-profile frequency-adjustable planar folded slot antenna (PFSA) system that is applicable to real-life smartphone platforms at the millimeter-wave (mmWave) 5G spectrum. Critical challenges that are attributed from the frequency discrepancy between sub-6 GHz and mmWave 5G are discussed. The multithrow topology is used to minimize the distortion of the far-field radiation pattern due to the beam squint while adjusting the resonant frequency between 27.95 and 28.65 GHz. The presented methodology entails using a multithrow switch chip directly on the transmission line, which enables a bistate function. The proposed methodology is exemplified into a 28 GHz $1 \times 4$ subarray. Measured and simulated results confirm that the frequency-adjustable PFSA features a 2.6-time enhanced impedance bandwidth and an average peak gain of 6.3 dBi while maintaining identical antenna volume in comparison to the previously reported PFSA.

Frequency-Stabilized Links for Coherent WDM Fiber Interconnects in the Datacenter

The continued growth in Hyperscale data center (HDC) deployment is expected to drive world-wide Internet traffic to an astounding 21 zettabytes by 2021. This growth will place increased demands on data center interconnects (DCIs) and drive the capacity of the underlying electronic application specific integrated circuit (ASIC) switch chips that route DCI ethernet traffic, from 12.8 Tbps per chip today to 100 Tbps and beyond in the future. This astounding growth will push the limits of today's incoherent fiber link technologies that connect switches, including power dissipation, density, and practical engineering solutions. To overcome these limits, high capacity coherent WDM, traditionally relegated to the metro and long-haul networks, will need to move into the DCI. However, migrating coherent WDM into the DCI, particularly for link distances less than 2 km, will require elimination of power consuming and costly technologies like the digital signal processor (DSP). Additionally, new photonic integration technologies will be needed to co-locate the coherent optical interfaces directly with switch ASICs to alleviate the bandwidth, power, and density limits. In this article, we introduce a new approach to DSP-free coherent WDM for the DCI called FRESCO: FREquency Stabilized Coherent Optical Links for Low Energy DCIs. FRESCO utilizes spectrally pure, ultra-stable light source technology, normally associated with high-end scientific applications like atomic clocks, to enable high capacity high-order WDM QAM with low bandwidth, low power electronics normally associated with RF links. Terabits per second FRESCO links based on shared, stabilized sources and high-density coherent WDM silicon photonic coherent transceivers that are co-located with the switch ASIC will pave the way to a DSP-free coherent WDM scalable DCI solution.

Virtualization in Programmable Data Plane: A Survey and Open Challenges

Programmable data plane (PDP) is an emerging technology for programming packet processing tasks by means of a domain-specific high-level language (e.g., programming protocol-independent packet processor (P4)) and programmable switch chips. Recently, several PDP virtualization schemes have been introduced to enable more flexible and elastic network management. In this article, we first give an overview PDP and P4. After that, existing PDP virtualization schemes are classified into hypervisor- and compiler-based approaches and their pros and cons are analyzed in detail. Finally, open challenges for PDP virtualization are identified and future research directions are presented.

TOSwitch: Programmable and High-Throughput Switch Using Hybrid Switching Chips

The future of networking switches and routers foresees in two key features: Programmability and Throughput. In this letter, we propose a Traffic Offload Switch (TOSwitch) model for such a versatile switch, using different breeds of switching chips, an ASIC and an FPGA, to achieve the above two key features. Our TOSwitch model is useful in many real-world use cases. The TOSwitch gives line-rate throughput and low latency for current and future network protocols. In our simulation on Xilinx Zynq 7000 (ONetSwitch45) FPGA board, the results show that the traffic offload model does not introduce considerable overhead in terms of latency, throughput and switching chip resources.