Switched-capacitor Circuits Research Articles

Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits

In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplifier followed by a class-B amplifier. The functionality of the class-B transconductance amplifier is dictated by a predefined hysteresis, and operates in parallel with the main amplifier. The proposed solution demands small static power (under 20% of main amplifier power) due to its class-B nature. The experimental results in a 40-nm CMOS technology show more than 45% reduction in slew time, and a 28% shorter slew time for 1% settling time when used in a typical 4.5 bit/stage block commonly used in pipelined analog-to-digital converters. Compared with the core amplifier, HD3 at 500 MHz reduces by more than 10 dB when the SR boosting circuit is activated.

CMOS Switched-Capacitor DSB-SSB Converter Using a Hilbert Transformer

The realization of an analog integrated circuit for conversion of double-sideband amplitude-modulated signals into single-sideband is presented. The converter is implemented by discrete-time switched-capacitor circuits, and it adopts structurally all-pass filters to realize a Hilbert transformer with low sensitivity to capacitor mismatch. The use of variable-gain amplifiers in place of frequency mixers greatly reduces circuit complexity and associated non-linearities. The chip is fabricated in a 180-nm CMOS technology with metal–metal capacitors. For 1.8-V power supply and 1-V differential input/output signals, experimental results show the converter achieves image rejection ratio (IRR) greater than 39.5 dB for lower-sideband modulation and 38.0 dB for upper-sideband modulation with input frequency ranging from 25% to 75% of the carrier frequency. Its silicon area is 1.09 mm $^{2}$ and the converter consumes only 17.7 mW for 1-MHz sampling frequency while its IRR presents standard deviation of only 0.5 dB among 20 chip samples without any circuit trimming.

Fully graph solution of the sensitivity of switched circuits

The most general parameter of the electronic circuit is its sensitivity. Sensitivity analysis helps circuit designers to determine boundaries to predict the variations that a particular design variable will generate in a target specifications, if it differs from what is previously assumed. There are two basic methods for calculating the sensitivity: matrix methods and graph methods. The method described in this article is based on a graph, that contains separate input ad output nodes for each phase. This makes it possible to determine the transmission sensitivity even between partial switching phases.The described fully-graph method is suitable for switched current circuits and switched capacitors circuits, too.

A 130 nm CMOS Power Management Unit With a Multi-Ratio Core SC DC–DC Converter for a Supercapacitor Power Supply

In recent years, switched capacitor (SC) DC–DC converters have been gaining interest as an attractive solution for implementing power management solutions in small scale low power systems, such as Internet of Things remote sensor nodes. Since switch capacitor circuits can be fully integrated in bulk CMOS technology, the number of external components is reduced, thus decreasing both the production costs and the volume of the system. This brief presents a power management unit using a multi-ratio SC DC–DC converter, and its controlling circuits, designed in a 130 nm bulk CMOS technology occupying an area of 0.138 mm2. It provides a constant supply voltage of 0.9 V for a maximum output power of 1 mW, from an input supercapacitor voltage ranging from 1.2 to 2.3 V. The measured results show a conversion efficiency peak of 80.4%.

Humidity and temperature sensor system demonstrator with NFC tag for HySiF applications

Abstract. Hybrid System-in-Foil (HySiF) is one of the emerging branches of flexible electronics in which ultra-thin silicon chips are integrated with flexible sensors in polymeric foils (Elsobky et al., 2018; Alavi et al., 2018). Intensive attention was given to the implementation of flexible environmental sensing platforms for logistics and food packaging (Cartasegna et al., 2011; Liu et al., 2016). The aim of this work is the implementation of a sensor system demonstrator using HySiF components, namely an ultra-thin microcontroller chip in addition to an on-chip temperature and an on-foil humidity sensors. The measurement concept for the relative humidity sensor is measuring the capacitance difference between an off-chip (on the foil substrate) humidity dependent sensor capacitor, and another humidity independent reference capacitor. The electrical readout technique is based on the charge amplifier switched capacitor circuit. It is implemented using a commercially available microcontroller (EM microelectronics EM6819) which has the advantage of being available as single chips to enable post-processing steps such as backthining and chip embedding in a thin polymer package. Sensor and reference capacitors are homogeneously integrated on-foil. 400 and 30 µm thick microcontroller dies (MCU) are used in this application. The charge amplifier result is digitized using an internal 10-bit analog-to-digital converter (ADC). The 10-bit ADC is time multiplexed between the charge amplifier structure and the internal temperature sensor. Linear interpolation is used to fit the digital output of the ADC and calibrate the output of the sensor system. Readings of the humidity level and the temperature are written to an NFC tag (from the company EM microelectronics based on chip EM NF4) using the contact interface. Readings can be accessed using a customized android application on a smartphone.

Performance optimization methods for switched-capacitor biquadratic filters

Abstract A class of computer-aided optimization methods based on Differential Evolution (DE), Particle Swarm Optimization (PSO) and Nelder Mead algorithms applied to a switched-capacitor (SC) filter circuit design are investigated. Comparisons of these algorithms applied to a 4th order biquadratic two-channel filter bank CMOS design on 0.35 µm technology are made. The frequency responses of the biquadratic filters must match ideal responses in a finite number of iterations with a limited number of “particles”. The original and derived methods are evaluated on the base of their convergence progress and their reliability over different starting populations. An optimal design approach based on combining algorithms is derived as a more suitable and more reliable method for SC circuit optimization.

Improved DC–DC converter topology for high step‐up applications

A novel non-isolated dc–dc converter topology for high step-up applications is presented in this study. The input side of the proposed converter can be derived with the help of a zeta converter, replacing the two inductors of basic zeta by a coupled inductor with double windings. At the same time, the switched-capacitor circuits are constituted through the secondary side of coupled inductor and diode capacitors, which enhance the voltage gain without a large duty cycle. The proposed converter can isolate the dc current from the electric source when it is switched off, and the voltage stress of the active switch is restrained through a passive regenerative snubber. Both the primary and secondary leakage energies of the coupled inductor can be recycled. The inrush current problem of diode capacitors is restrained by the leakage inductance of the coupled inductor. The above characteristics are the reason for the high-voltage gain and high efficiency of the converter. The principles of operation and steady-state analyses are described in detail. A compact circuit has been implemented in the laboratory, and the experimental results confirm the analysis of the presented converter.

A Bridge Modular Switched-Capacitor-Based Multilevel Inverter With Optimized SPWM Control Method and Enhanced Power-Decoupling Ability

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses.

A Modular Cell Balancer Based on Multi-Winding Transformer and Switched-Capacitor Circuits for a Series-Connected Battery String in Electric Vehicles

In this paper, a cell balancing topology for a series-connected Lithium-Ion battery string (SCBS) in electric vehicles is proposed and experimentally verified. In particular, this balancing topology based on the modular balancer consists of an intra-module balancer based on a multi-winding transformer circuit and an outer-module balancer based on a switched capacitor converter, both offering the potential advantages and over conventional balancing methods, including short equalization time, simple control scheme, elimination of voltage sensors. In addition, a number of cells in the SCBS can be easily extended in this circuit. Furthermore, a system structure and an operating principle of the proposed topology are analyzed and experimentally verified for three different cases. The voltages of all cells in the SCBS reached the balanced state regardless of the various arrangement of the initial voltage, where the energy efficiency of the circuit reached 83.31%. Our experimental realization of the proposed balancing topology shows that such a technique could be employed in electric vehicles.

A robust inverter‐based amplifier versus PVT for discrete‐time integrators

SummaryWith the reduction of the supply voltage in modern complementary metal‐oxide‐semiconductor technologies, and by their intrinsic class AB behavior, inverter‐based amplifiers are suitable to replace classical operational transconductance amplifiers in switched capacitor circuits like sigma‐delta modulators. This paper presents a new inverter‐based amplifier which increases the reliability versus process, voltage, and temperature variations. A new biasing stage is proposed, which controls the bias current without losing the class AB behavior thanks to the use of biasing transistors operated in linear region and a slew rate enhancement circuit. This makes this amplifier more robust than simple inverters regarding to process, voltage, and temperature variations, reducing the worst‐case bias current spread from +140% to +20%, while costing only 15% consumption increase and keeping inverter dynamic strengths.

A Voltage Equalizer Circuit to Reduce Partial Shading Effect in Photovoltaic String

Partial shading is one of the main causes in reducing the output power of photovoltaic (PV) systems. This paper proposes a circuit to recover the energy of shaded PV modules during partial shading condition (PSC). The proposed circuit, which is a combination of a buck–boost converter and the switched-capacitor (BBSC) circuits, equalizes the voltage of PV modules and prevents bypass diodes from bypassing the shaded modules in a string. Hence, shaded PV modules can have a contribution in output generated power instead of being bypassed. The main features of the BBSC are the utilization of the reduced number of switches in comparison with buck–boost and switched-capacitor circuits, a simple switching control strategy, and fast voltage equalization. In addition, a BBSC circuit is almost a lossless circuit during uniform shading conditions. To validate the effectiveness of the proposed BBSC circuit, both simulation results in PSCAD/EMTDC software and experimental results are presented.

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width W P range of 3 to 35 µm the average W N / W P ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits

ABSTRACTThis paper presents a low-power inverter-based gain-boosted operational transconductance amplifier (OTA) for switched capacitor (SC) circuits operating at higher supply voltage (>1 V). The proposed OTA is implemented using UMC 180 nm CMOS technology with a supply voltage of 1.8 V and it offers a high dc gain with a unity gain bandwidth (UGB) suitable for audio applications. All the transistors of the proposed OTA are operated in sub-threshold region to minimize the power consumption. Gain-boosting technique is employed to achieve a higher dc gain. The post-layout simulations demonstrate the robust performance of the proposed OTA, which delivers a high dc gain of 109.3 dB and a UGB of 5.29 MHz at 81° phase margin (PM) with a capacitive load of 2.5 pF for a typical process corner at room temperature (27°C). The proposed OTA draws a quiescent current () of 4.79 µA, resulting in a power consumption of 8.62 µW.

Switched-capacitor high-speed emulator for real-time fault location in electrical power systems

This research presents a discrete-time transmission line model based on the propagation of travelling waves. In this approach, the transmission line is emulated by means of many interconnected unit delay cells implemented with switched-capacitor (SC) circuits. The accuracy and limitations of this method is compared to existing transconductance–capacitor solutions and is evaluated in the frame of a novel power network fault location method based on the electromagnetic time-reversal principle. The impact of the non-ideal effects associated to analog CMOS SC circuits, such as amplifier finite gain, offset and switch charge injection is evaluated in the same context. A possible application of the model for the simulation of interconnected or multi-conductor lines is also discussed. After an AMS 0.35 µm process implementation, it is shown that the present method allows a fault location within 1% resolution and is a hundred times faster than nowadays digital solutions. This speed improvement allows a fault location within 160 ms, making thus real-time applications realistic.

A Reliable Strong PUF Based on Switched-Capacitor Circuit

This paper presents a highly reliable and invasive-attack-resistant switched-capacitor (SC) strong physical unclonable function (PUF), which can offer an extremely large number of challenge–response pairs. Two symmetrical capacitor arrays that are controlled by challenges are used to realize the strong ability of SC PUF. The mismatch created by the capacitor arrays in real fabrication is sampled by an SC circuit and further amplified by a latch-styled sense amplifier. By covering the entire chip with the metallic transmission lines connected to the sampling capacitor, the PUF can resist invasive attacks. To provide highly reliable responses, a built-in self-test (BIST) strategy is also adopted. A test capacitor is embedded in the PUF circuits to automatically test the capacitance deviation of the SC circuit. Only when the capacitance deviation is large, the output of the PUF is selected for use. The proposed strong SC PUF circuit is fabricated and verified using HJ standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that after using the BIST strategy, the bit error rate is less than $10^{-9}$ when the ratio of the selected responses is 19.6% for the PUF instances in our test.

A Chopping Switched-Capacitor RF Receiver With Integrated Blocker Detection

A 0.1–0.6 GHz chopping switched-capacitor (SC) RF receiver (RX) with an integrated blocker detector features a tunable center frequency, a programmable filter order, and a high out-of-band (OB) linearity. RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping are achieved with passive SC circuits only. The 34–80 mW 65-nm RX achieves 35-dB gain, +31 dBm OB-third-order input intercept point, +15 dBm B1dB, and 4.6–9 dB NF. The 0.2-mW integrated blocker detector detects large OB blockers with only 1- $\mu \text{s}$ response time. The filter order can be adapted to blocker power with the blocker detector.

High‐speed analogue sampled‐data signal processing for real‐time fault location in electrical power networks

The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.

A wide tuning range Gm-C complex filter with master-slave automatic frequency tuning based switched-capacitor

A wide tunable Gm-C complex filter with programmable operational transconductance amplifier (OTA) is presented in this paper. With automatic tuning of the master-slave stage, the filter's time constant C∕Gm is set to a fixed value. Programmable OTA prevails wider tunable range. To achieve high linearity, an optimized differential OTA structure based on second-generation current conveyors (CCIIs) is employed for achieving wider tuning range in the complex filter. And the linearity of the filter suffers less from the master frequency tuning circuit because of no modification in the inner V-I conversion core during the tuning course. Benefited from the virtual ground created by the amplifier in switched-capacitor circuit, higher tuning accuracy is obtained. The prototype of the filter was fabricated in SMIC 0.18-μm CMOS process. Measurement results show that the tunable center frequency ranges from 147 kHz to 1.95 MHz and the tunable bandwidth ranges from 94 kHz to 1.96 MHz. Meanwhile, the filter achieves an in-band IIP3 above 18.2 dBm.

Analysis of switched-capacitor circuits using driving-point signal-flow graphs

This paper extends the driving-point signal-flow graphs to switched-capacitor (SC) circuits by introducing a new theoretical element: an auxiliary voltage source that transfers no charge. In contrast to existing SFG methods, our method has no restrictions as to what types of SC circuits can be analysed, it requires no equivalent circuits or tables, and it works with two-phase as well as multi-phase SC circuits of any complexity. Compared to charge-equation matrix methods, it requires more effort, but is better suited for hand analysis because it makes causal relationships visible. Three illustrative examples are given to show the efficiency of the method and present a few application hints: a voltage doubler, the standard SC integrator, and a four-phase circuit simulating an inductor.

Design Methodology of High-Order Feed-Forward ΔΣ Modulators for Broadband Communications

This paper presents a design methodology to optimize high order Feed-Forward (FF) Delta-Sigma (ΔΣ) modulators architectures intended for use in next generations wireless applications. Being a low power and a low noise basic building block, the Telescopic OTA circuit is optimized using an algorithmic driven methodology to implement the switched capacitor (SC) integrator which constitutes a fundamental component of the designed FF ΔΣ modulator. A 2-1-1 cascaded FF ΔΣ modulator is firstly, designed for WCDMA and WLAN standards. The FF ΔΣ modulator performances are improved by implementing a 2-2 cascaded FF ΔΣ modulator. Both system-level and transistor-level simulations were performed with MATLAB and ORCAD PSPICE (AMS 0.35µm CMOS process). The 2-1-1 and the 2-2 cascaded FF ΔΣ modulators implemented with optimized SC circuits achieve respectively SNRs of 50dB and 56.3dB with over-sampling ratio of 16 for WCDMA standard.