Switched Capacitor Array Research Articles

CTC and CT5TEA: An advanced multi-channel digitizer and trigger ASIC for imaging atmospheric Cherenkov telescopes

We have developed a new set of Application-Specific Integrated Circuits (ASICs) of the TARGET family (CTC and CT5TEA), designed for the readout of signals from photosensors in cameras of Imaging Atmospheric Cherenkov Telescopes (IACTs) for ground-based gamma-ray astronomy. We present the performance and design details. Both ASICs feature 16 channels, with CTC being a Switched-Capacitor Array (SCA) sampler at 0.5 to 1GSa/s with a 16,384 sample deep storage buffer, including the functionality to digitize full waveforms at arbitrary times. CT5TEA is its companion trigger ASIC (though may be used on its own), which provides trigger information for the analog sum of four (and 16) adjacent channels. Since sampling and triggering takes place in two separate ASICs, the noise due to interference from the SCA is suppressed, and allows a minimal trigger threshold of ≤ 2.5 mV (0.74photo electrons (p.e.)) with a trigger noise of ≤ 0.5 mV (0.15p.e.). For CTC, a maximal input voltage range from −0.5V up to 1.7V is achieved with an effective bit range of > 11.6bits and a baseline noise of 0.7 mV. The cross-talk improved to ≤ 1% over the whole −3 dB bandwidth of 220MHz and even down to 0.2% for 1.5V pulses of 10 ns width. Not only is the performance presented, but a temperature-stable calibration routine for pulse mode operation is introduced and validated. The resolution is found to be ∼ 2.5% at 33.7 mV (10p.e.) and ≤ 0.3% at 337 mV (100p.e.) with an integrated non-linearity of < 1.6mV. Developed for the Small-Sized Telescope (SST) and Schwarzschild-Couder Telescope (SCT) cameras of the Cherenkov Telescope Array Observatory (CTAO), CTC and CT5TEA are deployed for both prototypes and shall be integrated into the final versions.

Characterization and performance of an upgraded front-end-board for NectarCAM

This paper presents an analysis of the updated version of the Front-End Board (FEB) for the NectarCAM camera, developed for the Cherenkov Telescope Array Observatory (CTAO). The FEB is a critical component responsible for reading and converting signals from the camera’s photo-multiplier tubes into digital data and generating module-level trigger signals. This study provides an overview of the design and performance of the new FEB version, including the use of an improved NECTAr3 chip with advanced features. The NECTAr3 chip contains a switched capacitor array for sampling signals at 1 GHz and a 12-bit analog-to-digital converter (ADC) for digitization upon receiving a trigger signal. The integration of the new NECTAr3 chip results in a significant reduction of NectarCAM’s deadtime by an order of magnitude compared to the previous version. The paper also presents the results of laboratory testing, including measurements of timing performance, linearity, dynamic range, and deadtime, to characterize the new FEB’s performance.

A wide locking range injection‐locked frequency divider with an auto‐adjusted injection bias

AbstractThis paper presents a Ku‐band divide‐by‐2 direct injection‐locked frequency divider (ILFD) with a wide locking range (LR) and high input sensitivity. The proposed ILFD incorporates an auto‐adjusted injection bias that uses a power detector (PD) to convert the power of the injected signal to a DC voltage. The bias voltage of the injection transistor is then auto‐adjusted in response to the output of the PD. The proposed ILFD employs a 2‐bit switched capacitor array to further enhance the entire LR. Implemented in a 65‐nm CMOS process, the experimental results show that the proposed ILFD achieves an LR of 62.3% (10.5–20 GHz) and 51.2% (11.2–18.9 GHz) at 0 and −10 dBm injection power, respectively. The proposed ILFD consumes 3.6 mW from a 0.6 V supply, and the core area is 0.067 mm2.

A wide-tuning range low phase noise LC-VCO with a high Q switched capacitor array

A wide-tuning range low phase noise LC-VCO with a high Q switched capacitor array

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

A Full-Waveform Digitizer for the Readout of Plastic Scintillator Detectors at HIRFL and HIAF

Being among the world’s leading heavy-ion scientific facilities, the heavy ion research facility in Lanzhou (HIRFL) and the high-intensity heavy-ion accelerator facility (HIAF) are constructed to study nuclear physics, atomic physics, nuclide chart, and heavy-ion related applications. Plastic scintillator detectors (PSD) are highly desirable and are used in large amounts for performing the experiments at HIRFL and HIAF. The PSDs are coupled with a photomultiplier tube (PMT) or silicon photomultiplier (SiPM) for converting the photons into electric signals. In this work, we develop a 16-channel full waveform digitizer (FWD) as a standard readout unit for the PSDs at HIRFL and HIAF. The FWD is based on two DRS4 chips. The design of these chips is based on the principle of a switched capacitor array (SCA), which can sample the analog signals at the GHz scale with low power consumption. In addition, the proposed FWD is designed with a general-purpose technique to reduce the development time, production cost, and maintenance difficulties. The laboratory test results show that the proposed FWD is relatively less nonlinear, i.e., about 0.6%. Its time precision is better than 15 ps. The cascade of multiple channels successfully realizes a sampling depth of 2048 cells. The joint test results of PSD show that an excellent performance in terms of measuring the cosmic rays is achieved. This paper presents the design and performance of the proposed FWD.

A Low-Voltage Class-D VCO with Implicit Common-Mode Resonator Implemented in 55 nm CMOS Technology

This paper presents a Class-D voltage-controlled oscillator (VCO) with a hybrid switch capacitor array. In order to reduce the phase noise of the oscillator, an implicit common-mode resonance technique is used, effectively suppressing the conversion of power supply noise to VCO phase noise. At the same time, due to the use of a transformer in implicit common-mode resonance technology, the core area of the oscillator is not significantly increased compared with the traditional Class-D VCO. Based on the proposed technology, the proposed VCO exhibits lower phase noise compared to the original Class-D VCO, and also has many different advantages compared to low-voltage VCOs produced by similar technological processes. The proposed VCO was designed in a 55 nm CMOS process. Simulation results show that this VCO has an operating range from 4.36 to 6.43 GHz, resulting in the frequency tuning range (FTR) of 38.5%. In addition, its power consumption was 3.46 mW, the phase noise at 4.36 GHz was −124.2 dBc/Hz@1 MHz, and the figure of merit (FoM) was −191.6 dBc/Hz@1 MHz. The core area is 0.15 mm2.

A high-speed transient waveform sampling SCA ASIC prototype in 180 nm CMOS technology

Switched capacitor array (SCA) is an important method of waveform digitization in high-energy physics experiments. This paper presents the design and test results of an eight-channel SCA ASIC for high-speed waveform sampling. The ASIC is designed and fabricated in 180 nm CMOS technology. The sampling rate of up to 14.25 Gsps is achieved by adopting the proposed dual-chain interpolating delay cell in DLL. The ASIC can be configured to operate in two modes: long-chain mode for deeper sampling depth and ping-pong mode for recording two waveforms in a short time. The bandwidth is over 1.1 GHz. By optimizing the sampling order, the distortion caused by the bandwidth discontinuity is reduced. Deep N-well is adopted to isolate the interference between digital and analog signals. The test results show that the random noise is approximately 0.87 mV RMS after the fixed-pattern noise correction. The time resolution is better than 5 ps RMS over the time measurement range of approximately 73μs.

A 12.3–18.5-GHz Single-Core Oscillator Using a Dual-Mode Variable Inductor With a Tunable Self-Resonant Frequency Technique

This article presents a single-core broadband voltage-controlled oscillator (VCO), employing a dual-mode variable inductor (VID). By configuring two independent switched-capacitor arrays embedded into a magnetically coupled LC network with a moderately magnetic coupled coefficient, the frequency tuning range (FTR) is improved by the wide inductance reconfigurable range of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${X}$ </tex-math></inline-formula> -type mode. Together with 2-bit conventional switched-capacitor banks, the VCO measures an FTR of 40.25% from 12.5 to 18.3 GHz. The low-quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> ) degradation characteristic of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> -type mode is utilized to implement the tuning bands calibration (TBC). After calibration, the tuning voltage can always be calibrated within a small range around the common voltage. The ultimate turning band covers the frequency drift caused by the temperature variation. Designed and fabricated in 65-nm CMOS technology, the measured phase noise after 1/2 division is −114.7 dBc/Hz at 1-MHz offset from the 18.49-GHz carrier frequency. The VCO core exhibits average power dissipation of 9.6 mW from 0.75-V power supply and 0.053 mm2 die area, while the other circuits are powered by a 1.2-V supply.

Low-power high-dynamic-range analog front-end for picosecond waveform sampling ASICs

This short communication presents an analog front-end (AFE) circuit used in the switched-capacitor array (SCA) for the waveform sampling ASIC. The idea to use in SCA-AFE native transistors which are common in today’s CMOS technologies offers a feasible solution to the issue of achieving picosecond time resolution with a low supply voltage. The circuit features a MOS capacitor and a source follower both of which are implemented with the native transistors, and a simple rail-to-rail comparator. A prototype PISTWAVE1 ASIC is designed in a 55 nm CMOS with a single 1.2 V supply voltage, the experimental results show the ASIC achieves a dynamic range of 0.1∼1.1 V, a 65.3 dB signal-to-noise ratio (SNR) with voltage calibration and a less than 10 ps time resolution. The overall power consumption is less than 10 mW/channel at a sampling rate of nearly 6 GS/s.

A 39-GHz High Image-Rejection Up-Conversion Mixer in 65-nm CMOS for 5G Communication

This brief presents an up-conversion mixer with high image rejection ratio (IRR) for 5G mmWave communication. To achieve broadband IRR at mmWave frequency with high area efficiency, a current-mode second-order tunable notch filter embedded in a cascode radio frequency (RF) buffer is proposed to realize tracking of the pole and zero frequencies with the switch capacitor array. To address the local oscillator (LO) leakage and even-harmonic distortion, a double-balanced passive mixer is adopted. For better isolation and lower insertion loss, a capacitor-inductor-capacitor (C-L-C) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\pi }$ </tex-math></inline-formula> -type impedance network is introduced in the mmWave T/R switch, realizing the equivalent lumped quarter wave transmission line with high area efficiency. Fabricated in a 65-nm CMOS process, the up-conversion mixer consumes 48.6 mW from a 1.2-V supply. Within the 3-dB bandwidth from 36 to 40.6 GHz, the mixer has a peak conversion gain of 0 dB, and its measured output 1-dB gain compression point (OP1dB) varies from −3 to −1.8 dBm. With the proposed tunable notch filter, the up-conversion mixer achieves a measured IRR of more than 53 dBc from 36 to 40.6 GHz, with a peak value of 58 dBc at 38.2 GHz.

A Waveform Sampling Prototype ASIC for Picosecond-Level Time Measurement

This article presents the design and test results of a waveform sampling application-specific integrated circuit (ASIC) based on the switched capacitor array (SCA). It integrates eight differential-input channels, and each channel consists of a 256-cell capacitor array, 256 12-bit Wilkinson analog-to-digital converters (ADCs), and a serial data readout. A sampling rate of up to 5 Gsps is achieved with a low-jitter delay-locked loop (DLL). Two shared coarse counters running at the rising and falling edges of the reference clock are used to extend the time measurement range. Several crosstalk reduction strategies were adopted in the circuit design, especially in the clock generation circuit and the digitization circuit. The ASIC has been fabricated in 180-nm CMOS process. The test results show that the random noise is approximately 0.7-mV rms after the fixed-pattern noise correction and that the precision of waveform timing is better than 7-ps rms with the sampling interval correction.

An SCA ASIC-based multi-channel readout system for a prototype multi-purpose TPC at CSNS Back-n white neutron source

The back-streaming white neutron source (Back-n) at China Spallation Neutron Source (CSNS), which has excellent energy spectrum and good time resolution, provides superior conditions for neutron induced light charged particle tracking experiment. To track light charged particles, CSNS has proposed a project named Multi-purpose Time Projection Chambers (MTPC) and completed a 1519-channel prototype. A multi-channel readout system based on Switched Capacitor Arrays (SCA) waveform sampling ASIC was designed to meet the requirements of the prototype MTPC. This paper presents the structure of this readout system and the results of the beam test with MTPC at CSNS. Time of Flight spectrum of neutron beam and 3D-track of neutron induced light charged particles were successfully reconstructed. These test results prove the feasibility of large-scale MTPC.

A 64-channel high-time resolution digital waveform sampling electronic system based on DRS4 for positron burst annihilation lifetime measurement

Measurements of the positron burst annihilation lifetime place high demand on the time discrimination of electronics. DRS4 chips based on switched capacitor array technology (SCA) are used to develop an electronic system with a total (2048 + 256)-channel sampling rate up to 5.12 GSPS, which can provide better time resolution and flexible data processing. The electronic system is modular in design and includes a front-end waveform sampling module (WSM) with 32 waveform sampling boards, each with 64 input channels plus 8 additional channels(one per DRS4 chip) for time calibaion, in addition to a back-end data processing module (DPM). The fan-out circuit integrated with the DPM will fan out the T0 signal in multiple stages at the time of positron burst generation and provide a common starting time and trigger signal for every DRS4 chip in the WSM. In this electronic system, the jitter of T0 after three-stage fan-out is 18 ps. After DC offset correction and time interval nonuniformity calibration, the coincidence time resolution with other channels is about 21 ps (σ). In addition, we correct the time difference of different channels of different chips, which is caused by different trace lengths of the multi-level fan-out T0 signal and the different fabrication processes. The electronic system is used to evaluate a 64-pixel detector module, and the time resolution of the detection module is measured to be 44 ps (σ).

A Reconfigurable Balun-LNA and Tunable Filter With Frequency-Optimized Harmonic Rejection for Sub-GHz and 2.4 GHz IoT Receivers

A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4^{\mathbf {th}}$ </tex-math></inline-formula> -order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{S}_{{21}}$ </tex-math></inline-formula> ) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;\!\!\!-12.8$ </tex-math></inline-formula> dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{S}_{{21}}$ </tex-math></inline-formula> of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively.

The ultrafast pixel array camera system and its applications in high energy density physics.

Diagnostics in high energy density physics, shock physics, and related fields are primarily driven by a need to record rapidly time-evolving signals in single-shot events. These measurements are often limited by channel count and signal degradation issues on cable links between the detector and digitizer. We present the Ultrafast Pixel Array Camera (UPAC), a compact and flexible detector readout system with 32 waveform-recording channels at up to 10 Gsample/s and 1.8GHz analog bandwidth. The compact footprint allows the UPAC to be directly embedded in the detector environment. A key enabling technology is the PSEC4A chip, an eight-channel switch-capacitor array sampling device with up to 1056 samples/channel. The UPAC system includes a high-density input connector that can plug directly into an application-specific detector board, programmable control, and serial readout, with less than 5W of power consumption in full operation. We present the UPAC design and characterization, including a measured timing resolution of ∼20ps or better on acquisitions of sub-nanosecond pulses with minimal system calibrations. Example applications of the UPAC are also shown to demonstrate operation of a solid-state streak camera, an ultrafast imaging array, and a neutron time-of-flight spectrometer.

A 3.7-to-10 GHz Low Phase Noise Wideband LC-VCO Array in 55-nm CMOS Technology

This paper presents a four-core LC-VCO array in 55 nm CMOS technology. Based on the multi-core VCO array technology and the switched capacitor array technology, the tuning range is expanded, and the phase noise optimization in a wide tuning range is achieved based on the second harmonic noise filtering technology and the Q value degeneration technology, as well as the optimization of the capacitor array switching transistors. The proposed VCO array, occupying a chip area of 1.65 × 1.44 mm2, realizes a measured oscillation frequency range of about 3.7−10 GHz with phase noise of −127.5~−116.08 dBc/Hz at 1 MHz frequency offset, and achieves an output power of 2.69 dBm from a total power consumption of 52.8 mW.

A Variable Gain Power Amplifier Based on Switched-Capacitor Array With Stable Linearity

This brief proposes a variable gain power amplifier (VG-PA) with stable linearity for n257/n258 frequency band applications. A switched-capacitor array is proposed in the cascode (CC) circuit to control the gain while maintaining linearity. A compensation inductor is introduced between the common-emitter (CE) and common-base (CB) transistors to suppress the phase variation. For the proof of concept, the VG-PA was fabricated in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS technology with a core size of 0.59 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 0.46 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurements show that at 24/26/28/29.5 GHz, over 5.7/5.5/7.0/7.5-dB gain tuning range, the output 1-dB compression point (OP1dB) is better than 14 dBm with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta }$ </tex-math></inline-formula> OP1dB less than 1.2 dB, the third-order output intercept point (OIP3) is better than 22 dBm with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta }$ </tex-math></inline-formula> OIP3 less than 3.4 dB, and the phase variation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta }{\varphi }$ </tex-math></inline-formula> ) is from 3 to 9.5°. To the author’s best knowledge, this work has the lowest linearity variation among Si-based variable gain amplifiers at millimeter-wave frequency band.

A Switched Capacitor Waveform Digitizing ASIC at Cryogenic Temperature for HPGe Detectors

This article presents the design and evaluation of the first cryogenic switched capacitor array (SCA)-based waveform digitizer (CryoSCA) for HPGe detectors for low-background physics experiments. The chip has integrated 16 channels and was fabricated using a 0.18- μm CMOS process with modified BSIM3v3 model parameters at 77 K. Each channel employs two 32-cell sample blocks working in the ping-pong mode, a 256-cell storage array, 32 parallel Wilkinson-type ADCs with 12-bits dynamic range, and registers. The chip was fully evaluated and showed promising performance at 300 K and 77 K. The measured power consumption of each channel increased from 3.3 mW at 300 K to 3.6 mW at 77 K. The averaging integral nonlinearity (INL) over 1-V dynamic range was measured to be 0.3% and 0.2% at 300 K and 77 K, respectively. The static noise decreased from 0.8 mV at 300 K to 0.6 mV at 77 K. The leakage current decreased from 18.2 fA at 300 K to 2.2 fA at 77 K.

Design of prototype readout electronics system for gamma-gamma collider

The γγ collider is proposed in China to observe γγ scattering and the Breit Wheeler (BW) pairs production.This paper presents a prototype readout electronics system that is intended to provide a suitable readout solution for the γγ collider. The paper analyzes the readout requirements of electronics such as implementation of 1426 electronical channels in a limited space, stability in vacuum working environment and incident particle discrimination. To meet the requirements, the paper proposes a high-density, low-power and high-sampling-rate (1 GHz) prototype readout electronics system using waveform digitization technology based on switch capacitor array (SCA) DRS4 chips and analog-to-digital converters (ADC). The prototype readout system is composed of 8 front-end electronics (FEE) boards and a data acquisition (DAQ) board. The FEE board can digitize 180-channel signals from the collider and send packaged data to the DAQ board via high-speed optical fiber. The paper proves the particle discrimination ability and the stability of the prototype electronics system in the joint-test with other detectors, which provides a strong guarantee for the subsequent development of the γγ collider.