Abstract
Switched capacitor array (SCA) is an important method of waveform digitization in high-energy physics experiments. This paper presents the design and test results of an eight-channel SCA ASIC for high-speed waveform sampling. The ASIC is designed and fabricated in 180 nm CMOS technology. The sampling rate of up to 14.25 Gsps is achieved by adopting the proposed dual-chain interpolating delay cell in DLL. The ASIC can be configured to operate in two modes: long-chain mode for deeper sampling depth and ping-pong mode for recording two waveforms in a short time. The bandwidth is over 1.1 GHz. By optimizing the sampling order, the distortion caused by the bandwidth discontinuity is reduced. Deep N-well is adopted to isolate the interference between digital and analog signals. The test results show that the random noise is approximately 0.87 mV RMS after the fixed-pattern noise correction. The time resolution is better than 5 ps RMS over the time measurement range of approximately 73μs.
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