Switched-capacitor Architecture Research Articles

A 0.8-μW and 74-dB High-Pass Sigma-Delta Modulator With OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition.

This work presents a third-order high-pass sigma-delta modulator (HPSDM) for biomedical signal acquisition. The operational amplifier (op-amp) sharing and noise-coupling techniques are adopted to reduce the required quantity of op-amps and add a noise-shaping order, which can achieve low power consumption and high resolution. A novel switched-capacitor architecture is proposed to suppress the increasing in-band noise and alleviate the circuit sensitivity to capacitor mismatch in the high-pass integrator. The proposed HPSDM was fabricated in a 0.18-μm standard CMOS process. Measurement results reveal that the proposed HPSDM has a signal-to-noise and distortion ratio (SNDR) of 75.26/74 dB in 200 Hz bandwidth and consumes 1.52/0.8 μW under 1.2/1 V supply voltage, which can achieve a peak Schreier Figure-of-Merit of 156.45/157.98 dB and a peak Walden FoM of 0.802/0.488 pJ/conv.

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of half-bridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of <inline-formula> <tex-math notation="LaTeX">$70\,\,\mu \text{m}\,\,\times 180\,\,\mu \text{m}$ </tex-math></inline-formula>. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40&#x0025; drop in power losses in the half-bridge circuit.

Reconfigurable Photovoltaic Emulator for Differential Diffusion Charge Redistribution Solar Modules

Evaluating, validating, testing, and performing research on hardware components that are connected to actual solar photovoltaic systems can be challenging; photovoltaic emulators are a common practical approach. In particular, addressing emulation for the crucial research topics of partial shading and cell mismatch is important. Differential diffusion charge redistribution is a switched-capacitor architecture using differential power processing for performing maximum power point tracking with cell-level granularity using only a single module-level converter. Among the prohibitive challenges is preventing damage to the module-embedded integrated circuits for the corner cases during fault and failure testing of connected hardware components including power converters. Emulators not only benefit research, but also product development and manufacturing of hardware components and power converters. This paper investigates a reconfigurable linear emulator with an analog controller for photovoltaic modules configured for differential diffusion charge redistribution. Cell mismatch and partial shading are shown to be equivalent and that the averaged behavior of these switched-capacitor solar photovoltaic modules can be represented by two separate continuous-time circuits that are coupled by feedback and constraints leading to an emulator design that is demonstrated through a hardware prototype.

Design and Characterizations of the Radiation-Hardened XCR4C ASIC for X-Ray CCDs for Space Astronomical Applications

Correlated double sampling (CDS) circuits are essential to processing the X-ray charge-coupled devices (CCDs) that have been widely used in the modern X-ray astronomical field. For timing observations, both energy resolution and timing resolution are of great importance. We are developing the XCR4C application-specific integrated circuit (ASIC), which is a fully customized four-channel radiation-hardened CDS ASIC targeting the readout of X-ray CCDs, for future space astronomical missions. The ASIC is implemented in a differential switched-capacitor architecture, making it highly linear, low power, immune to common-mode noise and interferences, as well as easily configurable. To combat the harsh low-earth-orbit space environment, some radiation-hardening techniques are applied, including the process hardening method, even-finger double-side bulk butting, and pseudo-double guard ring layout techniques. The XCR4C ASIC was fabricated with 0.35- $\mu \text{m}$ 2P4M CMOS technology with an epitaxial layer. The ASIC achieves a maximum 23-ppm integral nonlinearity and 5.8 e− rms equivalent noise charge under a typical 1-MHz pixel rate and only consumes 50 mW approximately from a single 3.3-V supply voltage. The results from radiation hardness assurance testing show that the ASIC has at least a total ionizing dose tolerance of 300 krad(Si), and no single-event latchup has been found up to a linear energy transfer of $81.35~\text {MeV}\cdot \text {cm}^{2}$ /mg with a total fluence up to $1.68\times 10^{7}$ ions/cm2.

A 0.5-V-supply, 37.8-nW, 17.6-ppm/°C switched-capacitor bandgap reference with second-order curvature compensation

This paper presents a switched-capacitor (SC) bandgap reference (BGR) with second-order curvature compensation for ultra-low power systems. The gate-source voltage of a sub-threshold MOSFET is proposed to implement the second-order curvature compensation voltage in this work. And then, a SC network is used, not only to add the second-order voltage and the first-order one together, but also to fulfill the summing weight effectively and precisely. In this way, the silicon area and power consumption can be reduced simultaneously. Furthermore, the design methodology of summing weight is investigated, and thus the temperature coefficient (TC) can be significantly reduced. The proposed SC-BGR was implemented and simulated in a CMOS 0.18 μm process, the average output voltage is 426.1 mV, achieving a TC of 17.6 ppm/°C from −20 to 100 °C under a 0.5 V minimum supply voltage. With the help of the SC architecture, a small chip area of 0.0975 mm2 is achieved with only 37.8-nW power consumption.

Analysis and Design of a Thermoelectric Energy Harvesting System With Reconfigurable Array of Thermoelectric Generators for IoT Applications

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- $\mu \text{m}$ CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients.

Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC---DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc---dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).

Point-of-load switched-capacitor DC-DC converter for distributed power systems

Integrated circuit (IC) of point-of-load DC-DC converter is presented. It is intended mainly for use in distributed power systems as a stand-along IC or as an on-chip block of the system-on-chip. The converter is based on multiphase switched-capacitor architecture and implemented in commercially available, 180 nm bulk-CMOS process. The paper discusses features of output voltage control in the multiphase system over a wide range of input and output voltages and load currents as well as output noise reducing techniques. The results of the test samples evaluation are presented.

On Chip DC-DC Converter with High Switching Frequency and Low Ripple Voltage

Objectives: A novel On Chip switched capacitor architecture to produce multiple voltages with high switching frequency and low ripple voltage. Methods: The proposed architecture uses integration of more than one converter topology to produce the scalable output voltage. The converter consists of MOSFET switches and MOS charge-transfer capacitors. The control circuitry was designed completely with digital domain to reduce static power consumed. Findings: The simulation of the scalable DC-DC converter was performed using TSMC 90nm Technology .The maximal efficiency of 80% was achieved for different topologies with 364 MHz switching frequency. Improvements: The load driving capacity of this converter was up to 5uW.

DC–DC Converter for Dual-Voltage Automotive Systems Based on Bidirectional Hybrid Switched-Capacitor Architectures

Automotive embedded electronic systems have been increasing in power and complexity and, therefore, more advanced power electronic converters are necessary in these vehicles. Several dual-voltage (42 V/14 V) bidirectional converter architectures have been proposed for automotive systems in recent years. However, most of them have low efficiency or are based in series and parallel configurations with large number of semiconductors and magnetics devices. Therefore, in this paper, we propose a bidirectional high-efficiency converter with lower number of components. This converter was created by merging a switched-capacitor converter and a conventional bidirectional converter, resulting in a hybrid topology. The voltage across the semiconductors of the proposed converter is equal to half of the highest voltage source value. Furthermore, the topology is composed of only one inductor to control the power flow between the two voltage sources. To verify all the mentioned features, a prototype was implemented experimentally, reaching a maximum efficiency of 97.5%.

A compact MMC submodule structure with reduced capacitor size using the stacked switched capacitor architecture

Modular multilevel converters (MMCs) are being developed for the grid connection of offshore wind or tidal farms. In order to reduce the construction and maintenance costs, it is desirable to reduce the weight and volume of the system. In current MMC submodule designs, the reservoir capacitor usually accounts for over 50% of the total volume and 80% of weight. This paper presents a new design concept and control principle for a submodule using the stacked switched capacitor (SSC) architecture that can significantly reduce the capacitor size in an MMC. Practical considerations for a high-voltage high-power SSC-based MMC submodule are presented in this paper, through the design of a 21-level, 40-kV (pole-pole dc), 19.1-MW, grid-connected system, and the concept is demonstrated experimenttally on a scaled-down 400-V, 12.3-Apeak laboratory prototype submodule. It is shown that with the proposed SSC architecture, the total volume of capacitors in each submodule can be reduced by more than 40% without significantly increasing the power loss.

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

In this paper, we propose a comparator-based switched-capacitor (CBSC) architecture using a multi-level input tracking preset voltage scheme. The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC). A multi-level preset voltage tracks the input voltage in order to improve the conversion rate without consuming additional power. Additionally, a comparator, current sources, and a feedback capacitor are shared to reduce the power and area of this cyclic ADC. Near the Nyquist-rate, a prototype implemented in 0.18 μm CMOS technology has a signal-to-noise and distortion ratio of 53.69 dB and a spurious-free dynamic-range of 62.36 dB, while consuming 0.73 mW of power.

Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm

Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multiplying digital-toanalog converter (MDAC) is proposed to present residue amplification by β (1 < β < 2). The redundancy of non-binary ADCs with radix β tolerates the non-linear conversion errors caused by the offsets of comparators, the mismatches of capacitors, and the finite DC gains of amplifiers, which are used in the MDAC. We also employed a radix value estimation algorithm to obtain an effective value of β for non-binary encoding; it can be realized by merely adding a simple conversion sequence and digital circuits. As a result, the power penalty of a high-gain wideband amplifier and the required accuracy of the circuit elements for a high-resolution ADC were largely relaxed so that the circuit design was greatly simplified. The implemented ADC achieves a measured peak signal-to-noise-and-distortionratio (SNDR) of 60.44 dB, even with an op-amp with a poor DC gain (< 50 dB) while dissipating 780 μW in analog circuits at 1.4 V and occupying an active area of 0.25 × 0.26 mm2. key words: Non-binary ADC, Cyclic ADC, Radix value estimation algorithm, β expansion, Multiply-by-β MDAC

An Input-Feedforward Multibit Adder-Less $\Delta{-}\Sigma$ Modulator for Ultrasound Imaging Systems

This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems. The delta-sigma modulator is based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer. The designed modulator has the advantages associated with input-feedforward architecture, such as the reduced output swing of the integrator, which relaxes the amplifiers' design requirements. Due to the power and area overheads and the timing constraint of the active adder in the conventional multibit input-feedforward modulator, we use an adder-less input-feedforward delta-sigma architecture. As a result, the designed architecture eliminates the extra power consumption and silicon area required by the adder. The designed architecture also relaxes the timing requirement for the quantizer and the dynamic element-matching block compared with the conventional delta-sigma modulator. The modulator achieves a dynamic range of 76dB and a peak signal-to-noise-plus-distortion ratio of 72.3 dB in a signal bandwidth of 6 MHz. The power consumption is 18.5 mW with 1.2-V supply voltage, and the chip core size is 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The energy required per conversion step is 0.46 pJ/conv.

A closed-loop MEMS accelerometer with capacitive sensing interface ASIC

A closed-loop MEMS accelerometer with capacitive sensing interface ASIC (application specific integrated circuit) is presented. The parasitic-insensitive switched-capacitor sample-charge architecture is used to implement the capacitive sensing, which is crucial to the case where sensor and interface ASIC are combined in a two-chip approach to implement the closed-loop MEMS accelerometer. Based on the 0.35 µm CMOS sensing interface ASIC, an accelerometer prototype has been implemented, in which force-rebalance with the lag-proportional–integral controller is applied to improve the system stability and frequency response performance, and the testing results indicate the sensitivity of the presented accelerometer is 650 mV/g, the full measurement range ±15 g, the non-linearity 0.098% and the noise floor 23.17 µg/rt-Hz.

Design of High-SNR CMOS Interface Circuit for Micro-Machined Gyroscope

A CMOS integrated interface circuit for micro-machined gyroscope containing a novel front-end and 6th-order Sigma-delta modulator is presented in this paper. To reduce the noise coming from the sensor and circuit, the front-end is accomplished by a switched-capacitor architecture, which constructed by a high-gain fully-differential amplifier and improved by chopper-stabilization technique, and work under a designed charging and sampling logic scheme. A cascade 6th-order Sigma-Delta modulator is designed to get high resolution, reduce quantized error and suppress the instability brought by high-order modulator. With the cascade structure and 16-bit resolution 32 OSR, the modulator outputs 3-bits digital stream. The whole circuit is designed with AMS technique and 3.3V power consumption. The simulation result presents that the interface circuit performs a appointed under a low-noise design specification in signal band, and the SNR of the circuit achieves remarkable value of 106dB.

Continuous-Time Input Pipeline ADCs

Two continuous-time input pipeline ADC architectures are introduced. The continuous-time input approach overcomes many of the challenges associated with a pure switched-capacitor architecture. The resistive input load of the two new architectures provides a benign interface to external drive circuitry. The switched-capacitor sampling function is moved to the second stage input which greatly eases the sampling distortion requirements and obviates the need for an explicit front-end sample-and-hold function. The second ADC presented additionally provides inherent anti-alias filtering, allowing the possibility of eliminating costly anti-alias filters. This second architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. Measured results obtained from two proof of concept test chips fabricated in a 0.18 μm CMOS process validate the effectiveness of the proposed techniques.

A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS

This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

Defect Identification in Large Area Electronic Backplanes

We describe a rapid testing system for active matrix thin-film transistor (TFT) backplanes which enables the identification of many common processing defects. The technique spatially maps the charge feedthrough from TFTs in the pixel and is suited for pixels with switched-capacitor architecture.

Internal jitter noise measurement procedure of a switched capacitor circuit

In this paper, an original method to estimate the internal jitter of a discrete time Sigma Delta modulator is presented. As internal jitter measurement of this component is difficult, a simple test circuit using the same switched capacitor architecture is developed. It means that the elementary blocks used to design this test circuit are the same ones used in the Sigma Delta (ΣΔ) modulator. The method used to estimate the internal jitter is based on the well-known ‘locked histogram method’ which consists on using the same frequency for the sine wave generator and the clock generator. A statistical analysis of the output signal provides the statistical properties of all noise contributions (thermal noise, generator noises and internal jitter). By using different frequency test values and with the help of the least square method, the statistical properties of the internal jitter noise is extracted.