Internal jitter noise measurement procedure of a switched capacitor circuit

Abstract

In this paper, an original method to estimate the internal jitter of a discrete time Sigma Delta modulator is presented. As internal jitter measurement of this component is difficult, a simple test circuit using the same switched capacitor architecture is developed. It means that the elementary blocks used to design this test circuit are the same ones used in the Sigma Delta (ΣΔ) modulator. The method used to estimate the internal jitter is based on the well-known ‘locked histogram method’ which consists on using the same frequency for the sine wave generator and the clock generator. A statistical analysis of the output signal provides the statistical properties of all noise contributions (thermal noise, generator noises and internal jitter). By using different frequency test values and with the help of the least square method, the statistical properties of the internal jitter noise is extracted.