An Input-Feedforward Multibit Adder-Less $\Delta{-}\Sigma$ Modulator for Ultrasound Imaging Systems

Abstract

This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems. The delta-sigma modulator is based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer. The designed modulator has the advantages associated with input-feedforward architecture, such as the reduced output swing of the integrator, which relaxes the amplifiers' design requirements. Due to the power and area overheads and the timing constraint of the active adder in the conventional multibit input-feedforward modulator, we use an adder-less input-feedforward delta-sigma architecture. As a result, the designed architecture eliminates the extra power consumption and silicon area required by the adder. The designed architecture also relaxes the timing requirement for the quantizer and the dynamic element-matching block compared with the conventional delta-sigma modulator. The modulator achieves a dynamic range of 76dB and a peak signal-to-noise-plus-distortion ratio of 72.3 dB in a signal bandwidth of 6 MHz. The power consumption is 18.5 mW with 1.2-V supply voltage, and the chip core size is 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The energy required per conversion step is 0.46 pJ/conv.