Cascaded Sigma-Delta modulator with dual quantization architecture and an inter-stage feedback path

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The conventional Sigma-Delta modulators have several drawbacks: e.g. the major problem with dual quantization architecture is that it can only be applied in a single loop topology, which causes the dynamic range (DR) problem; The inter-stage feedback topology only cancels nonlinear errors by introducing multi-bit DAC in its final stage. However, the rest of the stages still contain DAC nonlinearity errors without any noise shaping, which still degrade overall system performance. We propose a new structure, specifically a third-order (1-2) cascaded Sigma-Delta modulator with two 1-bit quantizers and an inter-stage feedback path. The main advantage is its 6dB reduction of total output noise power as compared with a conventional second-order Sigma-Delta modulator. We derive the output expression of various Sigma-Delta modulators in closed form. The advantage of the proposed modulator is confirmed by a system level simulation program.