Switch Block Research Articles

Universal switch blocks for three-dimensional FPGA design

The authors consider the switch-block design problem for three-dimensional FPGAs. A three-dimensional switch block M with W terminals on each face is said to be universal if every set of nets satisfying the dimension constraint (i.e. the number of nets on each face of M is at most W) is simultaneously routable through M. A class of universal switch blocks for three-dimensional FPGAs is presented. Each of the switch blocks has 15W switches and switch-block flexibility 5 (i.e. FS=5). It is proved that no switch block with less than 15W switches can be universal. The proposed switch blocks are compared with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that the proposed universal switch blocks improve routabilty at the chip level. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area.

On optimal hyperuniversal and rearrangeable switch box designs

This paper explores theories on designing optimal multipoint interconnection structures, and proposes a simple switch box design scheme which can be directly applied to field programmable gate arrays (FPGAs), switch box designs, and communication switching network designs. We present a new hyperuniversal switch box designs with four sides and W terminals on each side, which is routable for every multipin net-routing requirement. This new design is proved to be optimum for W = 1, ..., 5 and close to optimum for W /spl ges/ 6 with 6.3 W switches. We also give a formal analysis and extensive benchmark experiments on routability comparisons between today's most well-known FPGA switch boxes like disjoint switch blocks (Xilinx XC4000 Type), Wilton's switch blocks, Universal switch blocks, and our Hyperuniversal switch boxes. We apply the design scheme to rearrangeable switching network designs targeting for applications of connecting multiple terminals (e.g., teleconferencing). Simply using a /spl kappa/-sided hyperuniversal switch block with a W /spl times/ W crossbar attached to each side, one can build a three-stage one-sided polygonal switching network capable of realizing every multipoint connection requirement on kW terminals. Besides, due to the fine-grained decomposition property of our design scheme, the new switch box designs are highly scalable and simple on physical layout and routing algorithm implementations.

Investigation of six-membered carbocyclic compounds as a molecular switch block of room temperature phosphorescence in nondeoxygenated β-cyclodextrin solution

An aerated aqueous solution, intense room temperature phosphorescence (RTP) of nitrogen heterocyclic compounds (NHCs) and polyaromatic hydrocarbons (PAHs) can be observed when micro amounts of six-membered carbocyclic compounds (6-MCCs) are introduced in β-cyclodextrin (β-CD) solution. In order to find the predominating factors of the enhanced phosphorescence observed with this novel approach, 22 typical phosphors of NHCs and PAHs were carefully screened and served as model compounds. The role of the inner heavy atom, the substituent group and the host–guest molecules space-matching on the RTP of different phosphors were investigated. The results demonstrated that the enhancement effects of cyclohexane, bromocyclohexane and cyclohexanol for the RTP of NHCs and PAHs have precedence over traditional halide alkanes such as 1,2-dibromoethane (DBE), exhibiting an obvious sequence as following: cyclohexane > bromocyclohexane > cyclohexanol. This new approach compared with other RTP methods is simple, convenient and fast.

Reduction design for generic universal switch blocks

A k -side switch block with W terminals per side is said to be a universal switch block (( k , W )-USB) if every set of the nets satisfying the routing constraint (i.e., the number of nets on each side is at most W ) is simultaneously routable through the switch block. The (4, W )-USB was originated by designing better switch modules for 2-D FPGAs, such as Xilinx XC4000-type FPGAs, whereas the generic USBs can be applied in multidimensional or some nonconventional 2-D FPGA architectures. The problem we study in this article is to design ( k , W )-USBs with the minimum number of switches for any given pair of ( k , W ). We provide graph models for routing requirements and switch blocks and develop a series of decomposition theorems for routing requirements with the help of a new graph model. The powerful decomposition theory leads to the automatic generation of routing requirements and a detailed routing algorithm, as well as the reduction design method of building large USBs by smaller ones. As a result, we derive a class of well-structured and highly scalable optimum ( k , W )-USBs for k ≤ 6, or even W s, and near-optimum ( k , W )-USBs for k ≥ 7 and odd W s. We also give routing experiments to justify the routing improvement upon the entire chip using the USBs. The results demonstrate the usefulness of USBs.

Comment on "Generic universal switch blocks"

M. Shyu et al. (2000) defined the well-structured symmetric switch block M/sub N,W/ and showed that M/sub N,W/ is universal for any pair of positive integers N and W. However, we find that this result is partially correct. In this paper, we show that, when N/spl ges/7, M/sub N,W/ is not universal for odd Ws (/spl ges/3) and it is universal for any even W.

Architectural design for multistage 2-D MEMS optical switches

Next-generation wavelength routing optical networks requiring optical cross connects (OXC) in the network have the ability to direct optical signals from any input interface to suitable output interfaces by configuring their internal embedded optical switch matrices. Microelectromechanical systems (MEMS) switches are regarded as the most promising technology to achieve such functionality. We consider the construction of a multistage MEMS switch network with single two-dimensional (2-D) MEMS switch blocks. A power loss model is developed that calls on a single MEMS block that is then used to develop the model for a three-stage Clos network. An effective model for maximum loss difference between calls is also developed. Based on these, the paper also proposes three connection patterns [Max + Min greedy (MMG), compressed extended generalized shuffle 1 (C-EGS-1), and compressed extended generalized shuffle 2 (C-EGS-2)] to connect outlet ports and inlet ports between two neighboring stages in a three-stage Clos network. These connection patterns are proved to be optimal and efficient enough to reach the minimums of both the maximum power loss of calls and the maximum loss difference between calls.

Generic universal switch blocks

A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M. In this paper, we present an algorithm to construct N-sided universal switch blocks with W terminals on each side. Each of our universal switch blocks has (/sub 2//sup N/) W switches and switch-block flexibility N-1 (i.e., F/sub S/=N-1). We prove that no switch block with less than (/sub 2//sup N/)W switches can be universal. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. To explore the area performance of the universal switch blocks, we develop a detailed router for hierarchical FPGAs (HFPGAs) with 5-sided switch blocks. Experimental results demonstrate that our universal switch blocks improve routability at the chip level. Based on extensive experiments, we also provide key insights into the interactions between switch-block architectures and routing.

Quasi-universal switch matrices for FPD design

An FPD switch module M with /spl omega/ terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of EA is at most /spl omega/) is simultaneously routable through M. Chang et al. (1996) have identified a class of universal switch blocks. In this paper, we consider the design and routing problems for another popular model of switch modules called switch matrices. Unlike switch blocks, we prove that there exist no universal switch matrices. Nevertheless, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size and show that their routing capacities converge to those of universal switch blocks. Each of the quasi-universal switch matrices of size /spl omega/ has a total of only 14/spl omega/-20 (14/spl omega/-21) switches if /spl omega/ is even (odd), /spl omega/>1, compared to a fully populated one which has 3/spl omega//sup 2/-2/spl omega/ switches. We prove that no switch matrix with less than 14/spl omega/-20 (14/spl omega/-21) switches can be quasi-universal. Experimental results demonstrate that the quasi-universal switch matrices improve routability at the chip level.

Wavelength conversion in optical packet switching

A detailed traffic analysis of optical packet switch design is performed. Special consideration is given to the complexity of the optical buffering and the overall switch block structure is considered in general. Wavelength converters are shown to improve the traffic performance of the switch blocks for both random and bursty traffic. Furthermore, the traffic performance of switch blocks with add-drop switches has been assessed in a Shufflenetwork showing the advantage of having converters at the inlets. Finally, the aspect of synchronization is discussed through a proposal to operate the packet switch block asynchronously, i.e. without packet alignment at the input.

WDM packet switch architectures and analysis of the influence of tunable wavelength converters on the performance

A detailed analytical traffic model for a photonic wavelength division multiplexing (WDM) packet switch block is presented and the requirements to the buffer size is analyzed. Three different switch architectures are considered, each of them representing different complexities in terms of component count and requirements to the components, it is shown that the number of fiber delay-lines, that form the optical buffer, can be substantially reduced by the use of tunable optical wavelength converters, thereby exploiting the wavelength domain to solve contention of optical packets. For a 16/spl times/16 switch with four wavelength channels per inlet, all at a load of 0.8, the number of delay-lines is reduced from 47 to 12 by use of tuneable optical wavelength converters. Apart from the number of delay-lines the physical buffer structure is analyzed with special attention to the possibilities offered by optics, i.e., the possibility of several outlets sharing the same physical buffer. For the three architectures presented here, a tradeoff in the buffer architectures is addressed: a buffer physically shared among an outlets requires many wavelengths internally in the switch block, whereas, architectures with buffers dedicated to each outlet require a smaller number of wavelengths.

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-/spl mu/m VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology. >

A 1.8 Gb/s GaAs optoelectronic universal switch LSI with monolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4*4 space-division switch. It uses a new multistage 2*2 switch block with small hardware and high-speed operation. It can be expanded to a 16*16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN. >

ESTABLISHING OPERATIONS AND REINFORCEMENT EFFECTS

Positive reinforcement procedures have had a major impact on educational programs for the developmentally disabled; nevertheless, variation in reinforcer effectiveness both within and across individuals is a common phenomenon. This study examined one class of variables--establishing operations--that might influence the effectiveness of reinforcers. Five developmentally disabled adult males participated. Responding on one of two motor tasks--switch closure or block placement--was assessed during baseline, satiation, and deprivation conditions with respect to three classes of consequences: small food items, music, and social praise. Deprivation and satiation conditions were constructed so as not to alter significantly the normal course of events in a subject's day. For example, food deprivation entailed scheduling sessions just prior to a subject's regular lunch, and social deprivation involved limiting a subject's access to social interaction for 15 minutes, during which time the subject had access to an assortment of other activities. Results showed that each stimulus class functioned as reinforcement with different degrees of effectiveness during satiation versus deprivation conditions. These results are discussed in light of previous research on enhancement of reinforcer efficacy as well as the assessment and identification of functional reinforcers, and implications are presented for future research and client habilitation.

A new class of shift-varying operators, their shift-invariant equivalents, and multirate digital systems

A class of linear, shift-varying operators that generalize the notion of N-periodicity is defined. It is shown that shift-invariant equivalents for these operators exist, and that the equivalence is in a strong sense, preserving both algebraic and analytic system properties. It is shown that multirate sampled-data systems, although not generally periodic, fall into this class. Kranc vector switch decomposition and block filter implementations for single-input, single-output multirate systems are connected under the unifying framework of shift-invariant equivalents, and this framework provides a way to extend them both to multi-input, multi-output systems. >