Switch Block Research Articles

Development of an All-SFQ Superconducting Field-Programmable Gate Array

Recent advances in fabrication complexity and density-especially for the Institute of Advanced Industrial Science and Technology (AIST) advanced process 2 (ADP2) process and the MIT Lincoln Lab (MITLL) SFQ5ee process and beyond-allow the implementation of a superconducting field-programmable gate array (SFPGA) with sufficient complexity to host a number of different programmed functions. We discuss design choices for an all single flux quantum SFPGA targeting these modern processes, making heavy use of passive transmission line (PTL) layers they provide. Various configurations for lookup tables, basic logic elements and timing schemes are shown, and a viable switch block implementation is discussed. Academic FPGA electronic design automation (EDA) tools are repurposed for mapping Verilog hardware description language (HDL) functions to the chosen SFPGA design, whilst HDL and electrical simulations are used to show its correct operation. We show simulations for programming and the operation of an SFPGA, and discuss die size requirements for practical implementation.

Core executive functions are selectively related to different facets of motor competence in preadolescent children

Background: Although accumulating evidence suggests that motor and cognitive development is interrelated, only a few studies have investigated links between executive function and motor control. Therefore, the present cross-sectional study examined the relationship between motor competences and core components of executive functioning, including inhibitory control, working memory and cognitive flexibility. Methods: In 89 preadolescent children, motor competences were assessed using the MOBAK-5 test battery. Additionally, all participants completed computer-based versions of the Flanker task, which included standard and switch blocks, and the 2-Back task. Results: Partial correlations (correcting for age, gender and body mass index) revealed that locomotor skills were associated with the adjusted hit-rate on the 2-Back task (r = 0.34) whereas object control was linked with conflict score on the Flanker task (r = −0.39). In contrast, there was no correlation between switch costs and motor competences. Conclusion: In preadolescent children, high competences in locomotor skills and object control skills are associated with high performance on specific executive function tasks. This finding supports the current view that motor competences and cognitive control share some common underlying processes.

Miniaturised multi‐beam‐controlled circular eight‐port beamforming network for long‐range UHF RFID hemispheric coverage

In this paper, a miniaturised multi-beam-controlled circular eight-port beamforming network for long-range ultra-high-frequency radio-frequency identification (UHF RFID) hemispheric beam-coverage systems (e.g. unmanned aircraft systems) is proposed. For multi-beam control and compact implementation, the proposed eight-port feeding network consists of an integrated beam-control block with a two-stage RF switch block, 12 quadrature hybrid couplers, and 12 90° phase shifters, and was designed and fabricated on a circular three-layer 1.2 mm FR-4 substrate. The diameter of the fabricated network is ~0.47 λ 0 at 915 MHz. The measured maximum insertion loss, and amplitude and phase imbalances of the fabricated network at the authorised UHF RFID frequency band (902-928 MHz) are ~4.5 dB, ± 1.3 dB, and ± 17.5°, respectively. An eight-element dipole antenna array with the proposed feeding network shows feasibility of hemispheric beam coverage by generating multiple beams simultaneously regarding port controls. Beam coverages, where the simulated realised gain is higher than 3 dBi, are ~180° and 130° at φ = 90 and 0°, respectively.

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers

Resistive Random Access Memory (RRAM)-based routing multiplexers, built using a one-level structure, are significantly more delay efficient than state-of-art SRAM-based implementations thanks to their lower achievable on-state resistance. In addition, the delay of RRAM-based multiplexers scales better with respect to input size than SRAM-based multiplexers. This property allows RRAM-based FPGA architectures to employ larger multiplexers than their SRAM-based counterparts, without generating any delay overhead. In this paper, we first evaluate at the circuit-level the delay improvements of a state-of-art RRAM-based multiplexer. Then, to unlock the potential of RRAM-based multiplexers, we propose three related FPGA architecture optimizations: (a) The routing tracks should be interconnected to Look-Up Table (LUT) inputs via a one-level crossbar, instead of through Connection Blocks and local routing; (b) The Switch Block (SB) should employ larger multiplexers; (c) Length-2 wires should be used instead of length-4 wires. When a classical architecture is considered for both SRAM and RRAM technologies, RRAM-based FPGAs can reduce area by 17 percent and delay by 32 percent with zero power overhead for a 40 nm technology. The proposed architectural enhancements can further improve area by 15 percent, delay by 10 percent and channel width by 13 percent. Combining RRAM technology and architectural enhancements, the proposed RRAM-based FPGA architecture improves Area-Delay Product by 57 percent and Delay-Power Product by 38 percent, as compared to a SRAM-based FPGA exploiting a classical architecture.

High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems

In this paper a hardware architecture of scalar multiplication based on Montgomery ladder algorithm for binary elliptic curve cryptography is presented. In the proposed architecture, the point addition and point doubling are performed in parallel by only three pipelined digit-serial finite field multipliers. The structure of multiplier with a low critical path delay is based on a parallel and independent computation of multiplication by power of the variable polynomial. The inversion operation is implemented by using an efficient architecture of Itoh–Tsujii inversion algorithm. To maximize the performance of the scalar multiplier, a clock switch block is used to manage the clock signal so that the circuit operates at its maximum frequency at different steps of the Montgomery ladder scalar multiplication algorithm. Implementation results of the proposed architecture on Virtex-5 XC5VLX110FPGA show that the execution time of the scalar multiplication for binary finite fields GF(2163) and GF(2233) are 5.08µs and 6.84µs respectively, which are better than those of other similar works.

High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.

Dissociative global and local task-switching costs across younger adults, middle-aged adults, older adults, and very mild Alzheimer's disease individuals.

A task-switching paradigm was used to examine differences in attentional control across younger adults, middle-aged adults, healthy older adults, and individuals classified in the earliest detectable stage of Alzheimer's disease (AD). A large sample of participants (570) completed a switching task in which participants were cued to classify the letter (consonant/vowel) or number (odd/even) task-set dimension of a bivalent stimulus (e.g., A 14), respectively. A pure block consisting of single-task trials and a switch block consisting of nonswitch and switch trials were completed. Local (switch vs. nonswitch trials) and global (nonswitch vs. pure trials) costs in mean error rates, mean response latencies, underlying reaction time (RT) distributions, along with stimulus-response congruency effects were computed. Local costs in errors were group invariant, but global costs in errors systematically increased as a function of age and AD. Response latencies yielded a strong dissociation: Local costs decreased across groups whereas global costs increased across groups. Vincentile distribution analyses revealed that the dissociation of local and global costs primarily occurred in the slowest response latencies. Stimulus-response congruency effects within the switch block were particularly robust in accuracy in participants in the very mild AD group. We argue that the results are consistent with the notion that the impaired groups show a reduced local cost because the task sets are not as well tuned, and hence produce minimal cost on switch trials. In contrast, global costs increase because of the additional burden on working memory of maintaining 2 task sets.

ON-state Reliability of Cu Atom Switch Under Current–Temperature Stress

The dc current-stress tolerance of the ON-state Cu atom switch is evaluated at elevated temperature. It is revealed that the reset-direction current stress causes time-dependent failures, which originate from the $E$ -field-driven diffusion of Cu in the conducting bridge. A new empirical lifetime estimation model, including the Joule heating effect, gives an allowable maximum current per atom switch of $I_{{\textrm {max}}}= 115~\mu \text{A}$ , which is large enough to satisfy the requirements for signal routing under currents that are average (18 $\mu \text{A}$ ) and peak (63 $\mu \text{A}$ ) in the reconfigurable switch block operated at 500 MHz at 125 °C.

Comment on “On Optimal Hyperuniversal and Rearrangeable Switch Box Designs”

Fan proposed a set of hyperuniversal switch blocks (HUSBs), called Fan’s (4, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${w}$ </tex-math></inline-formula> )-HUSBs in this paper. He also proved that his design with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${w}$ </tex-math></inline-formula> less than 6 was optimum. That is, they used the least switches to achieve hyperuniversal routability. However, we find a counter example to show that there is an unnecessary switch in Fan’s (4, 4)-HUSB. Namely, we propose a new (4, 4)-HUSB, water-molecule-shaped switch block (WMSB), proving (4, 4)-WMSB with 24 switches is optimal. Furthermore, we also propose optimal (4, 7)-WMSB, which is a (4, 7)-HUSB with 42 switches.

Morphological priming during language switching: an ERP study.

Bilingual language control (BLC) is a much-debated issue in recent literature. Some models assume BLC is achieved by various types of inhibition of the non-target language, whereas other models do not assume any inhibitory mechanisms. In an event-related potential (ERP) study involving a long-lag morphological priming paradigm, participants were required to name pictures and read aloud words in both their L1 (Dutch) and L2 (English). Switch blocks contained intervening L1 items between L2 primes and targets, whereas non-switch blocks contained only L2 stimuli. In non-switch blocks, target picture names that were morphologically related to the primes were named faster than unrelated control items. In switch blocks, faster response latencies were recorded for morphologically related targets as well, demonstrating the existence of morphological priming in the L2. However, only in non-switch blocks, ERP data showed a reduced N400 trend, possibly suggesting that participants made use of a post-lexical checking mechanism during the switch block.

Electric-Field-Induced Control and Switching of Block Copolymer Domain Orientations in Nanoconfined Channel Architectures

Successfully controlling and switching cylinder-forming diblock copolymer domain orientations located in nanoconfining channel architectures has been achieved by the application of electric fields. Two degenerate structures result when the block copolymer thin films are confined in intersecting crossed channels. Here, cylinder domains align in one of two energetically degenerate structures having orientations of 45° or 135° with respect to the channels in the crossed areas. Electric fields are then introduced to further control the orientation of microdomains in both as-cast and phase-separated films. The cylinder domains then become oriented parallel to the electric field, and a single structure is obtained in the crossed areas. Finally, by introducing quadrupolar electrodes, we demonstrate the ability to switch block copolymer domain orientations between the two degenerate structures. These results suggest many follow-on applications in fundamental polymer physical chemistry as well as new approaches for static and dynamic nanostructure design and control.

Tool length influences reach distance estimation via motor imagery in children with developmental coordination disorder

Purpose: Children with developmental coordination disorder (DCD) often have difficulties with planning and generating a precise visuospatial representation of intended actions and using motor imagery to mentally represent motor behavior. Here, we aimed to extend the investigation of motor imagery in children with DCD by exploring its use with an estimation of reach paradigm that combines action representation and extension of space with tools. Method: Two groups of 18 children with DCD and typically developing (TD) matched controls were tested with an estimation of reach paradigm using a 20-cm (Experiment 1) and 40-cm (Experiment 2) tool. Conditions involved estimations via motor imagery with their arm, tool, and a switch-block (SB) involving an abrupt change of space with an “extension” from arm to tool and a “retraction” from tool to arm. Results: No significant group differences were found with the 20-cm tool; however, with the 40-cm implement, children with DCD were significantly less accurate than their TD counterparts. Conclusions: Compared to TD children, those with DCD have more difficulty estimating reach distances using the longer of two tool lengths: 40 cm compared to 20 cm. This finding may be related to differences in quality of motor imagery and in the ability to create an effective internal model for action in this context. Furthermore, our results suggest that tool length may present an additional action processing constraint on children with DCD. Additional studies are necessary to determine other constraints that children with DCD have when integrating tool use with spatial judgments for reach actions, as well as provide rehabilitation insights that involve motor imagery combined with tool use.

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a generic three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of a polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx 4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the three-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize the number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved. Based on experiment results, we can determine the parameters of PFPGA for the VLSI implementation.

High-voltage pulsed generators for electro-discharge technologies

A high-voltage pulse technology is one of effective techniques for the disintegration and milling of rocks, separation of ores and synthesized materials, recycling of building and elastoplastic materials. We present here the design and test results of two portable HV pulsed generators, designed for materials fragmentation, though some other technological applications are possible as well. Generator #1 consists of low voltage block, high voltage transformer, high voltage capacitive storage block, two electrode gas switch, fragmentation chamber and control system block. Technical characteristics of the #1 generator: stored energy in HV capacitors can be varied from 50 to 1000 J, output voltage up to 300 kV, voltage rise time ∼ 50 ns, typical operation regime 1000 pulses bursts with a repetitive rate up to 10 Hz.Generator #2 is made on an eight stages Marx scheme with two capacitors (100 kV–400 nF) per stage, connected in parallel. Two electrode spark gap switches, operated in atmospheric air, are used in the Marx generator. Parameters of the generator: stored energy in capacitors 2÷8 kJ, amplitude of the output voltage 200÷400 kV, voltage rise time on a load 50÷100 ns, repetitive rate up to 0.5 Hz. The fragmentation process can be controlled within a wide range of parameters for both generators.

Towards development of an analytical model relating FPGA architecture parameters to routability

We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and the connection and the switch block flexibilities. The output is an estimate of the proportion of nets in a large circuit that can be expected to be successfully routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. We show that the model correctly predicts routability trends. We also present an example application to demonstrate that this model may be a valuable tool for FPGA architects. When combined with the earlier works on analytical modeling, our model can be used to quickly predict the routability without going through any stage of an expensive CAD flow. We envisage that this model will benefit FPGA architecture designers and vendors to quickly evaluate FPGA routing fabrics.

Routability optimization for crossbar-switch structured ASIC design

In the routing architecture of a structured application-specific integrated circuit (ASIC), the crossbar is one of the most area-efficient switch blocks. Nevertheless, a dangling wire occurs when there is a routing bend in a crossbar switch. Dangling wires incur longer wire lengths as well as a higher interconnection capacitance. In this article, we tackle dangling wire issues for structured ASIC routability optimization. We first propose a compact graph model for crossbar-switch routing. With our graph model, switch connectivity relations can be removed to keep the 2D structured ASIC routing graph efficient and to speed up the runtime of our routing algorithm. Furthermore, we propose a heuristic dangling-wire-avoidance routing framework containing deferred pin assignment, Steiner point reassignment, and anchor pair insertion in order to minimize dangling wires and channel width. Finally, in order to take routing bends and channel width into account simultaneously, we propose concurrent and sequential integer linear programming (ILP) formulations and ILP variable/constraint degeneration techniques. The experimental results demonstrate that our proposed heuristic routing framework reduces dangling wires by 19%, channel width by 38%, and wire length by 13% to VPR using the crossbar switch (VPR-C). In addition, our sequential ILP router reduces dangling wires by 38%, channel width by 40%, and wire length by 15% compared to VPR-C. Thus, the runtime efficiency of our sequential ILP router is attractive for crossbar-switch structured ASIC routing.

Combined Architecture/Algorithm Approach to Fast FPGA Routing

We propose a new field-programmable gate array (FPGA) routing approach, which, when combined with a low-cost architecture change, results in a 40% reduction in router runtime, at the cost of a 6% area overhead and with no increase in critical path delay. Our approach begins with PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where the signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. We explore approximately 165 000 FPGA switch block architectures, showing that the choice of the architecture has a significant impact on the complexity of the SAT formulation, and by extension, on routing runtime. Our approach points to a new research direction, namely, reducing FPGA computer-aided design runtime by exploring FPGA architectures and algorithms together.

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme

A multiple-valued data transfer scheme using X-net is proposed to realize a compact bit-serial reconfigurable VLSI (BS-RVLSI). In the multiple-valued data transfer scheme using X-net, two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. One cell composed of a logic block and a switch block is connected to four adjacent cross points by four onebit switches so that the complexity of the switch block is reduced to 50% in comparison with the cell of a BS-RVLSI using an eight nearest-neighbor mesh network (8-NNM). In the logic block, threshold logic circuits are used to perform threshold operations, and then their binary dual-rail voltage outputs enter a binary logic module which can be programmed to realize an arbitrary two-variable binary function or a bit-serial adder. As a result, the configuration memory count and transistor count of the proposed multiplevalued cell are reduced to 34% and 58%, respectively, in comparison with those of an equivalent CMOS cell. Moreover, its power consumption for an arbitrary 2-variable binary function becomes 67% at 800MHz under the condition of the same delay time. key words: multiple-valued data transfer scheme, X-net, multiple-valued current-mode logic, MOS current-mode logic, fine-grain reconfigurable VLSI

GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.