WDM packet switch architectures and analysis of the influence of tunable wavelength converters on the performance

Abstract

A detailed analytical traffic model for a photonic wavelength division multiplexing (WDM) packet switch block is presented and the requirements to the buffer size is analyzed. Three different switch architectures are considered, each of them representing different complexities in terms of component count and requirements to the components, it is shown that the number of fiber delay-lines, that form the optical buffer, can be substantially reduced by the use of tunable optical wavelength converters, thereby exploiting the wavelength domain to solve contention of optical packets. For a 16/spl times/16 switch with four wavelength channels per inlet, all at a load of 0.8, the number of delay-lines is reduced from 47 to 12 by use of tuneable optical wavelength converters. Apart from the number of delay-lines the physical buffer structure is analyzed with special attention to the possibilities offered by optics, i.e., the possibility of several outlets sharing the same physical buffer. For the three architectures presented here, a tradeoff in the buffer architectures is addressed: a buffer physically shared among an outlets requires many wavelengths internally in the switch block, whereas, architectures with buffers dedicated to each outlet require a smaller number of wavelengths.