Surrounding-gate Field-effect Transistors Research Articles

PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation

We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature.

Моделирование характеристик низковольтных вентилей на совмещённых цилиндрических полевых нанотранзисторах с полностью охватывающим затвором

The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.

Comparative Analysis of Different Figures of Merit for AlGaN/GaN and Si Surrounding-Gate Field Effect Transistors (SG-FETs)

The combination of better transport properties of III-V group semiconductors along with excellent electrostatic control of surrounding gate is a promising option for the future low power electronics. Accordingly in this brief, the major figures of merit (FOM) including output current, output conductance (gd), transconductance generation factor (TGF), intrinsic gain (dB), and dynamic power dissipation are computed for surrounding-gate field effect transistors (SG-FETs) considering III-V group semiconductors and Si channel material respectively with respect to different device parameters. It is noticed that the center potential is higher in AlGaN/GaN SG-FET than Si for different values of channel length (CL), channel height (H), oxide thickness (tox), and doping concentration (Nd). The AlGaN/GaN SG-FET provides lower gd than Si for different values of CL, H, tox, and Nd as required for MOS analog circuits to achieve higher gain. The peak value of TGF and intrinsic gain is higher in AlGaN/GaN than Si SG-FET for different values of CL, H, tox, and Nd. In this work, we have analyzed the MOSFET structure for normally off operation of AlGaN/GaN high electron mobility transistors (HEMTs) to reduce dynamic power dissipation (PD). The magnitude of PD is calculated to be lower in normally off AlGaN/GaN SG-FET than Si for different values of CL, H, and tox.

Evaluation of controlled strain in silicon nanowire by UV Raman spectroscopy

The evaluation of strain states in silicon nanowires (Si NWs) is important not only for the surrounding gate field-effect transistors but also for the thermoelectric Si NW devices to optimize their electric and thermoelectric performance characteristics. The strain states in Si NWs formed by different oxidation processes were evaluated by UV Raman spectroscopy. We confirmed that a higher tensile strain was induced by the partial presence of a tetraethyl orthosilicate (TEOS) SiO2 layer prior to the thermal oxidation. Furthermore, in order to measure biaxial stress states in Si NWs accurately, we performed water-immersion Raman spectroscopy. It was confirmed that the anisotropic biaxial stresses in the Si NWs along the length and width directions were compressive and tensile states, respectively. The Si NW with a TEOS SiO2 layer on top had a larger strain than the Si NW surrounded only by thermal SiO2.

Investigation of sub-10nm cylindrical surrounding gate germanium nanowire field effect transistor with different cross-section areas

In this paper, germanium nanowires (GeNWs) with different cross-sectional areas are considered as the channel of a cylindrical surrounding gate field effect transistors (CSG-FETs) and the electronic properties of them are calculated through the density functional method and Slater-Koster (SK) tight binding model. The corresponding transistor parameters are obtained using Non-equilibrium Green’s function (NEGF) combined by SK model. We find that SK model predicts the well-nigh same bandgap value compared to meta-GGA-DFT approximation, while GGA-DFT underestimates the value of the bandgap. CSG-GeNW-FETs Transistor figure of merit shows a supreme Ion/Ioff ratio which is equal to 1012 for one of the considered structures with a circular cross-section. The obtained sub-threshold swing (SS) values for the FETs illustrate an increment trend when the supercell size of the germanium nanowire increases whereas the transconductance and ON-current of the FETs decrease when the GeNW supercell size scales down due to the declining of the density of states and electron transmission spectrum.

Analytical Models for Electric Potential, Threshold Voltage, and Subthreshold Swing of Junctionless Surrounding-Gate Transistors

Analytical models for electric potential, threshold voltage, and subthreshold swing of the junctionless surrounding-gate field-effect transistors are presented. Poisson equation is solved and the electric potential is obtained. With the potential model, explicit expressions for threshold voltage and subthreshold swing are obtained. The analytical results are compared with those from simulations and excellent agreements are observed. The analytical models are useful not only for fast circuit simulations, but also for device design and optimization.

III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications

III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled growth of InAs, GaAs, and InGaAs NWs on Si by selective-area growth, and discuss how to control growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial growth with misfit dislocations and coherent growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

Characterization of Nanowire CMOS Amplifiers Using Fully Depleted Surrounding Gate Transistors

Vertical nanowire SGFETs (Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects and achieve extremely low OFF current. This paper presents the fully depleted BSIMSOI modeling of low power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics and potential applications of these transistors for high speed analog circuits. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 μA and 0.7 μA drain currents, 14 μA/V and 8 μA/V transconductances, 400 kΩ and 1.1 MΩ output resistances, 36 THz and 25 THz unity current gain cutoff frequencies and 120 THz and 100 THz maximum frequency of oscillations, respectively. The differential-pair amplifier realized with SGFETs dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40 dBm and -52 dBm, respectively, and the 3rd order intermodulation is -24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation VLSI technology.

Design of Next Generation Amplifiers Using Nanowire FETs

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates <TEX>$5{\mu}W$</TEX> power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 muA and 0.7 muA drain currents, 14 muA/V and 8 muA/V transconductances, 400 kOmega and 1.1 MOmega output resistances, 36 THz and 25 THz unity-current-gain cutoff frequencies, and 120 THz and 100 THz maximum frequency of oscillations, respectively. A single-stage CMOS SGFET amplifier dissipates 1.64 muW power and provides 500 GHz bandwidth with -6.5 gain and -24 dBm third-order intermodulation distortion tones for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The large-signal operation of the amplifier with 1 V output swing exhibits 2.2 ps delay, 5.4 ps rise time, and 4.7 ps fall time while oscillating at 30 GHz. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next-generation very-large-scale integration (VLSI) technology.

Design and Characterization of the Next Generation Nanowire Amplifiers

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

Silicon Vertically Integrated Nanowire Field Effect Transistors

Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.

Electrochemical synthesis of a ZnO nanowire field-effect transistor

ABSTRACTAluminum wires are electrochemically sculptured into bi-directional templates for the growth and contacting of nanowires as three terminal devices. The utility of this nanostructured micro-template is demonstrated by a ZnO nanowire surrounding gate field-effect transistor. This bottom-up approach to a 3-D nanowire transistor is unique in that it can be almost entirely fabricated in a beaker using aqueous, room-temperature electrochemistry.