Abstract
Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.
Highlights
The speed of silicon integrated circuits is reaching beyond 100 GHz to enable wireless communications with wideband channels [1]
Alternative silicon compatible transistor devices such as silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs), FinFETs, and nanotube FETs have been investigated for improved performance [2]
The layout views of a vertical nanowire surrounding gate field effect transistors (SGFETs) and a planar bulk MOSFET are shown in Figure 1 for comparison
Summary
The speed of silicon integrated circuits is reaching beyond 100 GHz to enable wireless communications with wideband channels [1]. Even though the current VLSI technology has approached to its scaling limits necessitating a replacement technology, silicon-based devices are still favored to realize large-scale circuits and systems because of their low cost. Downscaling of the bulk metal oxide semiconductor field effect transistors (MOSFETs) to nanometer dimensions has increased the leakage current and short-channel effects. Vertical surrounding gate field effect transistors (SGFETs) have full gate control around channel and have minimized short-channel effects [3]. The layout views of a vertical nanowire SGFET and a planar bulk MOSFET are shown in Figure 1 for comparison. Both transistors have identical channel widths of 13 nm and channel lengths of 10 nm and are designed with similar layout design rules. The area of the vertical transistor is (40 nm × 40 nm) 1600 nm, and the area of the planar transistor is 1600 nm (76 nm × 21 nm) with body contact
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