Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits

Abstract

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 muA and 0.7 muA drain currents, 14 muA/V and 8 muA/V transconductances, 400 kOmega and 1.1 MOmega output resistances, 36 THz and 25 THz unity-current-gain cutoff frequencies, and 120 THz and 100 THz maximum frequency of oscillations, respectively. A single-stage CMOS SGFET amplifier dissipates 1.64 muW power and provides 500 GHz bandwidth with -6.5 gain and -24 dBm third-order intermodulation distortion tones for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The large-signal operation of the amplifier with 1 V output swing exhibits 2.2 ps delay, 5.4 ps rise time, and 4.7 ps fall time while oscillating at 30 GHz. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next-generation very-large-scale integration (VLSI) technology.