Polar codes are the recently adopted error correction codes in the 5th generation new radio (5G NR) mobile communication standards. The hardware architecture for encoding and decoding plays a significant role in achieving channel capacity. The processing complexity due to successive cancellation (SC) algorithm is one of the limitations faced in the prior decoder architectures. In this study, semi-parallel architecture is employed which reduces the processing complexity. However, the partial-sum generation module in the conventional semi-parallel decoder occupies a larger space which in turn limits the operating frequency as code length N increases. A modified partial-sum computation model based on shift register (SR-PSU) is employed to improve the area utilization and maximum operating frequency. The SR-semi-parallel decoder is synthesized and implemented in a field-programmable gate array (FPGA) for code length up to N = 210. The proposed decoder shows a significant reduction in the critical path delay and processing complexity as compared to the conventional semi-parallel decoder.