Subtraction Circuit Research Articles

A Novel Method for Solution of the Division Operation on ARM7 Microcontroller

Before architecture V7, the hardware of ARM microcontroller family does not support division operation. Although it is easy to program on ARM processors with C language which can implement division operation with library functions, the procedure has much trouble and the efficiency is lower when the function code written in C language is called in assembly program. This paper introduces an algorithm for the division operation on ARM7 processor and also gives corresponding subroutines which can be used directly in assembly program design. The algorithm is similar to the operation theory of the digital circuit which uses subtraction circuit to do division operation. The given subroutines can deal with the division operation between two 32-bit unsigned integers and the division between a 64-bit unsigned integer and a 32-bit unsigned integer.

Research and Improvement of Leakage Protection System in Coal Winning Machine

Most of the Shearer adopt additional DC power protection, it has to protect a comprehensive, capacitive current compensation, the simple characteristics of action value of the tuning, however, it in the actual production will occur leakage protection device malfunction, tripping phenomenon For the leakage protection circuit in traction motor of coal winning machine is impacted by frequency converter devices in the course of their work, malfunctions appear frequently. This paper makes an in-depth analysis, analyzing the shortcomings of the current protection circuit, After the analysis of the interference signal, it is proposes a solution of using the subtraction circuit to offset interference signals and conducts a simulation analysis. The above scheme, which is simple and easily realized, can improve the reliability of leakage protection device in traction motor. Avoiding unnecessary production halts. The production efficiency can be improved.

A flexible current‐mode classifier circuit and its applications

AbstractIn this paper a new CMOS classifier circuit is presented, simulated, and compared with other recently introduced circuits. The proposed CMOS circuit operates in current‐mode and can classify several types of data. The architecture is designed using two threshold circuits and a subtraction circuit. Among many possible applications of the classifier circuit, template‐based pattern classification, namely template matching and character recognition with corruption, and in another direction its use as a quantizer are given. Using 0.35‐ µm AMS technology parameters, SPICE simulations as well as hard realization results for the classifier and application circuits are included; detailed Monte Carlo analyses to assess parameter mismatch effects are also performed. Copyright © 2010 John Wiley & Sons, Ltd.

Solid-state photon-counting hybrid detector array for high-resolution multi-energy X-ray imaging

We present in this article the development of a photon-counting, energy-discriminating modular detector based on a pixelated CdZnTe sensor coupled pixel-by-pixel to a novel Digital Pixel Sensor (DPS) readout. The detector is designed for munitions inspection, breast X-ray CT and SPECT/MRI. The current DPS design can also be used to read out other solid-state sensors. The prototype detector is 5.5 mm×5.5 mm in size, and consists of 19×19 pixels on a 250 μm pitch. The DPS is designed in a 0.35 μm process, and every pixel includes a preamplifier , a leakage-current subtraction circuit, an auto-zeroed programmable-gain stage, five comparators, a variable-delay reset circuit and five 16 bit counters. The module is expected to operate at high X-ray fluence exceeding 80 MHz/mm 2 , and to improve resolution and contrast in images, while significantly enhancing their signal-to-noise ratio, and assist in identifying material composition via dual-energy imaging. The detector design, fabrication and anticipated performance are discussed.

The Design, Implementation, and Preliminary Results of a New Photodetector for the DIII–D Thomson Scattering Diagnostic

A redesign of the Thomson scattering data acquisition system located on the DIII-D tokamak is undergoing its trial phase. The redesign was made necessary by several factors, including the desire to improve the quality of the acquired data. In addition, the previous generation system was based on CAMAC technology, which has become difficult to maintain and is no longer supported. A big part of this improved redesign comes from the use of faster electronics allowing for greatly improved background light subtraction, the main source of noise. The past system utilized LeCroy FERA CAMAC gated integrator modules for integration and digitization. The redesigned system takes a much more distributed approach. The new system consists of a number of subsystems, including photodetectors, digitizers, distribution panels, and timing circuits. The most significant upgrade was performed on the photodetector electronic assembly. A key feature was to make the units much more self-contained in regard to the preamplifier, background subtraction, integration, and bias circuits. The redesigned photodetectors and preliminary test results of the trial phase will be presented.

Arithmetic Circuits of Redundant SUT-RNS

The residue number system (RNS) is suitable for implementing high-speed digital processing devices because it supports parallel, modular, fault-tolerant, and carry-bounded arithmetic. The carry propagation is restricted to inside the modulus. The remaining intramoduli carry propagation limits the speed of arithmetic operation. Therefore, the carry-free property of a redundant arithmetic can be used. In this paper, we discuss a recently proposed class of high-radix redundant RNS based on the stored-unibit-transfer representation for modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1 that improves the power-delay-product performance of conventional redundant RNS. In addition, subtraction and multiplication circuits are designed in the proposed system.

Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part II

Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part IIWe continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the Redundant Signed Digit (RSD) operations, then prove its stability of the calculations. Generally, one-bit binary full adder assumes positive weights to all of its three binary inputs and two outputs. We define the circuit structure of two-types n-bit GFAs using the recursive construction to use the RSD arithmetic logical units that we generalize full adder to have both positive and negative weights to inputs and outputs. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: GFACIRC2, version: 7.8.09 4.97.1001

Eight-Bit Semiflash A/D Converter

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

Current Mode Monolithic Active Pixel Sensor With Correlated Double Sampling forCharged Particle Detection

A monolithic active pixel sensor operating in current mode for charged particle detection is described. The sensing element in each pixel is an n-well/p-sub diode with a PMOS transistor integrated in an n-well. The drop of the n-well potential from the collection of charge modulates the transistor channel current. Each pixel features two current mode memory cells. The subtraction of distant-in-time samples frees the signal of fixed pattern noise (FPN) and of the correlated low-frequency temporal noise components, resulting in extraction of the particle footprint. The subtraction circuits are placed at each column end. A transimpedance amplifier, integrating in sequence two current samples and subtracting the results in an arithmetic operation, was adopted. The integrated version of the transimpedance amplifier, designed with a maximized conversion gain, is burdened by a risk of an early saturation, imperiling its operation, if the dispersions of the dc current component are too big. The degree of dispersions could not be estimated during the design. Some number of columns is available as a backup with the direct current readout. An external realization of the subtracting circuit, based on the same principle, is used to process direct output columns. The concept of the data acquisition setup developed, the tested performance of an array of cells, and the processing circuitry are described

Hearing aid having acoustical feedback protection

Apparatus for use in a hearing aid wherein a first microphone is connected to the hearing aid case and exposed to free air and a second microphone is connected to the hearing aid case and sealed from free air. The audio inputs from the two microphones are applied to a subtractive circuit so as to cancel any audio signals transmitted through the case of the hearing aid while passing audio signals received by the microphone exposed to free air. In another aspect of the invention, a hearing aid of the behind-the-ear (BTE) type couples sound from the hearing aid loudspeaker through a hollow tube to an inner portion of the ear. A second hollow tube is coupled between a third microphone on the hearing aid case and an outer portion of the ear. Some sound emanating from the tube disposed in the inner ear, exits the ear and is picked up by the second tube and directed to the third microphone. The signal from the third microphone is nulled out by the electronic circuitry of the hearing aid. The gain and phase of the signals picked up by the second tube are automatically adjusted to provide the intended nulling and resulting minimization of acoustical feedback.

Delay-optimized implementation of IEEE floating-point addition

We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: a nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one's complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. We present technology-independent analysis and optimization of our implementation based on the Logical Effort hardware model and we determine optimal gate sizes and optimal buffer insertion. We estimate the delay of our optimized design at 30.6 FO4 delays for double precision operands (15.3 FO4 delays per stage between latches). We overview other IEEE FP addition algorithms from the literature and compare these algorithms with our algorithm. We conclude that our algorithm has shorter latency (-13 percent) and cycle time (-22 percent) compared to the next fastest algorithm.

Differential predictive floating-point analog-to-digital converter

Floating-point analog-to-digital converters (FP-ADCs) were developed and used to quantize wide dynamic range signals in applications where large signals need not be encoded with a precision greater than that required for small ones. Comparing floating point with uniform quantization, it was shown that FP-ADC provides smaller relative quantization error and higher dynamic range for the same resolution, but at the cost of doubling the conversion time. To improve the accuracy and speed of conversion of such an FP-ADC, a higher precision predictive floating-point architecture was conceived (PFP-ADC). The PFP-ADC consists of two parallel uniform A/D converters, a D/A converter, a fixed-gain amplifier and a subtraction circuit. The current subtrahend of the subtraction circuit is a prediction based on the previous acquisitions, while the current minuend is the measured signal itself. Determination of mantissa and exponent occurs in parallel. This paper presents both the principle used to improve the resolution of the FP-ADCs and the FPGA implementation of the PFP-ADC proof-of-concept.

Off-axis second-order high-T/sub C/ rf SQUID gradiometer for magnetocardiography in unshielded environment

We study an electronic gradiometer system for magnetocardiography (MCG) in unshielded environments. The electronically balanced gradiometer consists of three high temperature radio-frequency (rf) superconducting quantum interference device (SQUID) magnetometers, arranged in off-axis arrangement with the baseline of 6 cm to form the second order (2nd-order) gradiometer system. A set of coefficients were found to optimize the noise spectrum of the 2nd-order gradiometer via the fast Fourier transform technique by considering both the phase and the amplitude in the subtraction circuit. Besides, the signal of the 2nd-order gradiometer was filtered by notch and low frequency band pass filters. Hence, the field noise spectrum of the 2nd-order gradiometer was reduced to 1.5 pT/Hz/sup 1/2/ at 60 Hz, to 1 pT/Hz/sup 1/2/ at 10 Hz, and to 1.5 pT/Hz/sup 1/2/ at 1 Hz. We perform MCG measurements in unshielded environments. To enhance the signal to noise ratio, the measured MCG signals were averaged according to the simultaneously recorded electrocardiogram signals recorded simultaneously. The MCG measurement was performed over several locations above the thorax of a human being. Our results demonstrate that the off-axis arrangement can offer the flexibility in the design of the SQUID-based multichannel magnetocardiogram.

Fourier transform method for self-mixing interference signal analysis

Self-mixing interferometry (SMI) has been used to measure the distance and displacement. Although the principle of self-mixing interference is different conventional interference, we concluded that FFT analysis technique could also be used to detect the signal phase and increase the measurement precision of self-mixing interferometry. First the SMI signal is obtained by feeding the light from the target to cavity of laser diode, then it is pre-processed by an analog subtraction circuit to remove the overlapped output intensity due to the injection current modulation. Finally, SMI signal is analyzed by FFT phase detection method. Theoretical analysis and simulation calculations are presented. Experimentally, displacement of a PZT-driven target was measured with a precision of λ/50.

Stochastic neural computation. I. Computational elements

This paper examines a number of stochastic computational elements employed in artificial neural networks, several of which are introduced for the first time, together with an analysis of their operation. We briefly include multiplication, squaring, addition, subtraction, and division circuits in both unipolar and bipolar formats, the principles of which are well-known, at least for unipolar signals. We have introduced several modifications to improve the speed of the division operation. The primary contribution of this paper, however, is in introducing several state machine-based computational elements for performing sigmoid nonlinearity mappings, linear gain, and exponentiation functions. We also describe an efficient method for the generation of, and conversion between, stochastic and deterministic binary signals. The validity of the present approach is demonstrated in a companion paper through a sample application, the recognition of noisy optical characters using soft competitive learning. Network generalization capabilities of the stochastic network maintain a squared error within 10 percent of that of a floating-point implementation for a wide range of noise levels. While the accuracy of stochastic computation may not compare favorably with more conventional binary radix-based computation, the low circuit area, power, and speed characteristics may, in certain situations, make them attractive for VLSI implementation of artificial neural networks.

Transmission system utilizing different coding principles

In a transmission system for transmitting speech and music signals, an input signal is coded in a coder (11) by a time domain coder (4). The output signal of the time domain coder (4) is decoded by a time domain decoder (8) and the signal thus decoded is subtracted from the input signal by a subtracter circuit (10). To improve the coding quality, the difference signal is coded by a frequency domain coder (12) and the output signal of the time domain coder (4) and the frequency domain coder (12) are combined in a multiplexer (14) and transmitted to a receiver.

A modular current-mode classifier circuit for template matching application

In this work, a current-mode Euclidean distance calculator circuit is proposed to play the role of a classifier. This classifier circuit is designed based on a subtracter circuit, an absoluter circuit, a squarer/divider circuit, and a square-rooter/multiplier circuit. The modular design of this classifier allows it to be easily extended for classification application with more input dimensions by doing some proper signal-scaling work due to the dynamic range limited by the square-rooter/multiplier circuit. This classifier circuit has been fabricated with a 0.6 /spl mu/m single-polysilicon double-metal CMOS process. Both simulation results and measurements of the implemented chip are presented to confirm the function of this classifier.

NbN circuits and packaging for 10 Kelvin IR focal plane array sensor signal processing

Infrared (IR) focal plane array (FPA) imaging signal processing circuits, built in NbN and operating at 10 Kelvin, are presented. An ADC chip and digital signal processing chip are mounted on a 1.25 inch multi-chip module (MCM) with high bandwidth, low impedance interconnect. The populated MCM is designed to be installed into a module housing for operation with the cryogenic IR FPA. The 12-bit NbN SFQ counting ADC, previously used in a single chip version of the IR focal plane array sensor test system, is now implemented in an improved NbN process which includes a ground plane. Considerable attention has been focused on reducing parasitic inductance to compensate for the high characteristic inductance of the NbN films. These design improvements increase operating margins and circuit yield and make the ADC more robust in the presence of external system noise. Data from a bit-serial subtraction circuit to be used for pixel-by-pixel background subtraction is also presented. Finally, the design and electrical qualification of the physical package is described.

Phototransistors Using Point Contact Structures

We report on the photoresponse of point-contact structures under laser illumination conditions. The point contacts showed phototransistor action with high responsivity of more than 105 A/W and a high on-off rate, probably due to the efficient hole localization in the point contacts. We demonstrate an optical subtraction circuit using two point-contact phototransistors and an optical amplifier using a point contact phototransistor and a light-emitting diode.

A low-voltage, low-power CMOS fifth-order elliptic GM-C filter for baseband mobile, wireless communication

The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.