Subthreshold Swing Voltage Research Articles

Feasibility of Atomic Layer Deposited AlZrO<italic>x</italic>Film to Achieve High Performance and Good Stability of ZnSnO-TFT

In this paper, ZnSnO thin-film transistors (TFTs) with atomic layer deposited AlZrOx insulator of varying thicknesses are first fabricated. The electrical performance and thermal stability of ZnSnO-TFTs with different AlZrOx thicknesses are characterized. The 130-nm-thick AlZrOx-based TFT shows the optimized electrical properties. (Its mobility, threshold voltage, subthreshold voltage swing, and on–off ratio are 12.5 cm2/ $\text{V}\cdot \text{s}$ , 0.3 V, 0.15 V/dec, and $8 \times 10^{7}$ , respectively.) In addition, ZnSnO-TFT with 130-nm AlZrOx film under temperature stress shows a small negative threshold voltage shift of 1.2 V. Density of states is calculated by the temperature-dependent field-effect measurement. The improvement of temperature stability is attributed to the reduction of interface trap states and smooth AlZrOx surface. The results are further verified by the bias stability. It indicates that using atomic layer deposited AlZrOx as a gate insulator is an effective method to achieve high performance and good stability of ZnSnO-TFT.

Enhanced Reliability of Vertical Strained Impact Ionization MOSFET Incorporating Dielectric Pocket for Ultra-Sensitive Biosensor Applications

Fast switching with an enhanced reliability device structure of Vertical Strained Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) has been successfully design, simulated and analyzed in this paper. Ultra-low power with low subthreshold swing (S) and high breakdown voltage are imperative for ultra-sensitive biosensors. Impact ionization MOSFET (IMOS) is predicted to be capable of S as low as 20 mV/dec, which is much lower than Conventional MOSFET (CMOS). There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. S value for DP place at source side is higher (S 24.4 mV/decade) as compared at the drain side (S 18.9 mV/decade) intrinsic region. The vicinity of DP near the drain region reduces charge sharing effects associated with the source and thus improves impact ionization rate. The introduction of a Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the reliability of the device by attaining higher breakdown voltage. Consequently, with the reduced of alloy scattering, the electron mobility has been improved by 22%. In many aspects, it is revealed that the incorporation of DP enhanced the reliability of VESIMOS for future development of nanoelectronic devices.

Comprehensive review on the development of high mobility in oxide thin film transistors

Oxide materials are one of the most advanced key technology in the thin film transistors (TFTs) for the high-end of device applications. Amorphous oxide semiconductors (AOSs) have leading technique for flat panel display (FPD), active matrix organic light emitting display (AMOLED) and active matrix liquid crystal display (AMLCD) due to their excellent electrical characteristics, such as field effect mobility (μ FE ), subthreshold swing (S.S) and threshold voltage (V th ). Covalent semiconductor like amorphous silicon (a-Si) is attributed to the anti-bonding and bonding states of Si hybridized orbitals. However, AOSs have not grain boundary and excellent performances originated from the unique characteristics of AOS which is the direct orbital overlap between s orbitals of neighboring metal cations. High mobility oxide TFTs have gained attractive attention during the last few years and today in display industries. It is progressively developed to increase the mobility either by exploring various oxide semiconductors or by adopting new TFT structures. Mobility of oxide thin film transistor has been rapidly increased from single digit to higher than 100 cm2/V·s in a decade. In this review, we discuss on the comprehensive review on the mobility of oxide TFTs in a decade and propose bandgap engineering and novel structure to enhance the electrical characteristics of oxide TFTs.

Sub-10 nm Tunable Hybrid Dielectric Engineering on MoS2 for Two-Dimensional Material-Based Devices.

The successful realization of high-performance 2D-materials-based nanoelectronics requires integration of high-quality dielectric films as a gate insulator. In this work, we explore the integration of organic and inorganic hybrid dielectrics on MoS2 and study the chemical and electrical properties of these hybrid films. Our atomic force microscopy, X-ray photoelectron spectroscopy (XPS), Raman, and photoluminescence results show that, aside from the excellent film uniformity and thickness scalability down to 2.5 nm, the molecular layer deposition of octenyltrichlorosilane (OTS) and Al2O3 hybrid films preserves the chemical and structural integrity of the MoS2 surface. The XPS band alignment analysis and electrical characterization reveal that through the inclusion of an organic layer in the dielectric film, the band gap and dielectric constant can be tuned from ∼7.00 to 6.09 eV and ∼9.0 to 4.5, respectively. Furthermore, the hybrid films show promising dielectric properties, including a high breakdown field of ∼7.8 MV/cm, a low leakage current density of ∼1 × 10-6 A/cm2 at 1 MV/cm, a small hysteresis of ∼50 mV, and a top-gate subthreshold voltage swing of ∼79 mV/dec. Our experimental findings provide a facile way of fabricating scalable hybrid gate dielectrics on transition metal dichalcogenides for 2D-material-based flexible electronics applications.

Introduction of a metal strip in oxide region of junctionless tunnel field-effect transistor to improve DC and RF performance

Achieving steeper subthreshold slope and high ON–OFF current ratio (\(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\)) is essential for use of semiconductor devices in switching applications. It is well known that tunnel field-effect transistors face serious issues related to low ON-state current and poor radio frequency (RF) response. We report herein a unique method for realizing a sharp tunneling junction in a charge plasma-based junctionless tunnel field-effect transistor by embedding a metal strip in the oxide region near to the source–channel connection. This modulates the carrier concentration profile at the source–channel interface, making it abrupt. This steeper source–channel tunneling junction results in a reduced tunneling barrier and increased flow of charge carriers at the junction. Furthermore, electron transfer along the channel is accounted for using postprocessing based on the drift–diffusion equations as well as the band-to-band tunneling current. This phenomenon contributes to the improved direct-current (DC) characteristics of the device. Selection of a metal with an appropriate work function for the strip can improve the subthreshold swing and threshold voltage (\(V_{\mathrm{th}}\)) of the device. The increased charge carrier tunneling rate at the junction also results in a huge improvement in RF parameters of the device, including cutoff frequency (\(f_{T}\)), gain–bandwidth product, and transit time (\(\tau \)).

Low-voltage-drive and high output current InGaZnO thin-film transistors with novel SiO2/HfO2/SiO2 structure

ABSTRACTLow-voltage-drive InGaZnO (IGZO) thin-film transistor (TFT) with SiO2/HfO2/SiO2 (SHS) multilayer gate insulator is deposited by radio frequency sputtering at room temperature. The fabricated device performed a threshold voltage of 1.4 V, a field effect mobility of 8.6 cm2/VS, an Ion/Ioff ratio of 2.9 × 105, and a sub-threshold voltage swing of 0.67 V/dec. The drain current was 260 µA with both gate and drain voltage of 10 V. SHS multilayer has a high capacitance to increase the high mobility and decrease the drive voltage for TFT.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

β-gallium oxide (β-Ga2O3) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga2O3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga2O3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

Atomic layer deposition deposited high dielectric constant (κ) ZrAlOx gate insulator enabling high performance ZnSnO thin film transistors

The high κ ZrAlOx gate insulators were deposited by atomic layer deposition on silicon and characterized by the different analytical techniques. The grazing incidence X-ray diffraction (GIXRD) verifies that ZrAlOx thin films show an amorphous structure. The X-ray photoelectron spectroscopy (XPS) confirms that the form of ZrAlOx phase improves the electrical properties and stability of the associated devices. Then, all ZrAlOx thin films were integrated in metal-insulator-semiconductor structures to check the electrical capabilities. They all show a low leakage current density (about 1 × 10−8 A/cm2) under a high electric field of about 2.0 MV/cm, and exhibit a stable capacitance as a function of frequency. Their associated ZTO TFTs were deposited by a radio frequency sputtering, and the influence of the ZrAlOx thickness on the stabilities under positive bias stress and electrical properties is investigated. The 130 nm ZrAlOx based TFT shows the optimized electrical properties (its mobility, threshold voltage, sub-threshold voltage swing and on-off ratio are 12.5 cm2/V, 0.3 V, 0.15 V/dec. and 8 × 107 and the good stability with 2.5 V threshold voltage shift under the positive bias voltage stress. The better properties of 130 nm ZrAlOx based TFTs are attributed to a less interface trap states and surface scattering center.

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (ZrxSi1−xO2) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO2 and ZrO2 targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the ZrxSi1−xO2 film up to 600°C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr0.85Si0.15O2 dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81mV/dec), field-effect mobility (μFE=51.7cm2/Vs), and threshold voltage shift (ΔVTH=0.03V).

Improved performance of gate-last FDSOI tunnel field-effect-transistors (TFETs) with modulating Al2O3 composition in atomic layer deposited HfAlOx gate dielectrics

We have studied the electrical characteristics of both n-type and p-type fully depleted silicon on insulator (FD-SOI) tunnel field-effect transistors (TFETs) by modulating Al2O3 fraction (25%, 50%) within atomic layer deposited HfAlOx gate dielectric. Compared to HfO2 alone, lower subthreshold swing (S.S), higher Ion/Ioff, and stronger threshold voltage (Vth) immunity against electrical stress are obtained for both n-type and p-type TFETs by adopting nano-laminated atomic layer deposited HfAlOx, attributed to the increased band gap and interfacial layer scavenging effect.

Assessment of the Electrical Performance of Short Channel InAs and Strained Si Nanowire FETs

We present a numerical study aimed to benchmark short gate InAs nanowire-FETs (NW-FETs) against their strained Si (sSi) counterpart. Our full-quantum simulations focus on both gate-length scaling and device variability and include the impact of electron–phonon scattering and surface roughness (SR). Interestingly, we found that SR improves the subthreshold-voltage swing (SS) of short gate-length InAs devices by inducing a reduced source-to-drain tunneling. Hence, InAs NW-FETs exhibit a larger immunity to the roughness-induced degradation of the ON-current, whereas they suffer froma larger OFF-current and SS variabilitywith respect to the sSi ones. According to our results, InAs NW-FETs could compete with sSi NW-FETs only for very short gate lengths, when the device performance is significantly degraded, while for longer devices sSi NW-FETs remain a more effective and reliable choice due to the higher gate overdrive charge.

Improvement in interfacial characteristics of low-voltage carbon nanotube thin-film transistors with solution-processed boron nitride thin films

In this article, we demonstrate the potential of solution-processed boron nitride (BN) thin films for high performance single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) with low-voltage operation. The use of BN thin films between solution-processed high-k dielectric layers improved the interfacial characteristics of metal-insulator-metal devices, thereby reducing the current density by three orders of magnitude. We also investigated the origin of improved device performance in SWCNT-TFTs by employing solution-processed BN thin films as an encapsulation layer. The BN encapsulation layer improves the electrical characteristics of SWCNT-TFTs, which includes the device key metrics of linear field-effect mobility, sub-threshold swing, and threshold voltage as well as the long-term stability against the aging effect in air. Such improvements can be achieved by reduced interaction of interfacial localized states with charge carriers. We believe that this work can open up a promising route to demonstrate the potential of solution-processed BN thin films on nanoelectronics.

A New Design Approach of Dopingless Tunnel FET for Enhancement of Device Characteristics

Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for achieving better electrical behavior. This task is more challenging in the case of dopingless TFETs (DL TFETs). In this concern, we propose a novel design of DL TFET, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode (used for inducing p+ region) of conventional dopingless n-TFET to overcome the issue of low on-state current ( $\text{I}_{\mathrm{on}}$ ) due to presence of tunneling barrier. Proposed modification is helpful for achieving steeper tunneling junction at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface. The optimization for work function of the metal layer (ML) has been performed for improving $\text {I}_{\mathrm{on}}$ , point subthreshold swing and threshold voltage ( $\text {V}_{\text {th}}$ ). Finally, the impact of the ML misalignment from the gate/source terminal and optimization of its length is also presented.

2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software.

Carrier trapping anisotropy in ambipolar SnO thin-film transistors

The anisotropic carrier trapping behaviors was demonstrated for ambipolar tin monoxide (SnO) thin-film transistors (TFTs). On one hand, the TFTs exhibited good stability with almost no changes in transfer characteristics under negative gate-bias stress (NGBS). On the other, under positive gate-bias stress (PGBS), the transfer curves presented parallel and positive shift with no degradation in field-effect mobility and subthreshold voltage swing. The stress-time evolution of the turn-on voltage shift, induced by different positive stress voltages and temperatures, could be described by the stretched exponential model. The relaxation time was extracted to be 1.6×104s at room temperature with activation energy of 0.43eV, indicating that the ambipolar SnO TFTs under PGBS approach the stability of amorphous indium-gallium-zinc oxide based TFTs.

Zinc tin oxide thin film transistor: Effect on channel isolation and channel width

The n-channel field-effect thin-film transistors (TFTs) with amorphous zinc tin oxide as an active layer has been investigated. The transparent ZTO thin films deposited at room temperature using rf magnetron sputtering have an optical bandgap of 3.3 eV. Before the fabrication of TFT postdeposition annealing of the film was carried out 300°C for 1 hour. The channel layer on Si/SiO2 substrate was deposited in two different structures, isolating each device from the neighboring devices and without isolation. The isolation of active material improves TFT performance by reducing the gate leakage current and parasitic bias stress. The on-off ratio and subthreshold swing were significantly changed from 2.3x103 and 0.73 V/dec to 2.55x106 and 0.23 V/dec respectively on isolation. The effect of channel width on the TFT parameters such as saturated mobility, subthreshold swing and threshold voltage are also studied. The threshold voltage decreases with increasing channel width but mobility and subthreshold swing are relatively constant. The threshold voltage decreased from 19 V to 11 V when the channel width increased. It may be due to the increasing parasitic resistance between the source/drain contacts and the ZTO channel layer.

Enhanced Operation of Back-Channel-Etched a-IGZO TFTs by Fluorine Treatment during Source/Drain Wet-Etching

The effect of fluorine (F) treatment on operation of back-channel-etched (BCE), inverted staggered amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) is investigated. The F, in the form of ammonium fluoride (NH4F), is mixed with a hydrogen peroxide (H2O2)-based wet-etchant that is used to pattern source/drain Mo electrodes. X-ray photoelectron spectroscopy and secondary ion mass spectrometry reveal that the F penetrates into the a-IGZO bulk, effectively decreasing the concentration of surface hydroxyl groups that may, otherwise, be formed in abundance due to the presence of H2O2. As a consequence, device-to-device uniformity and operation of the BCE a-IGZO TFTs improves after the F treatment: The turn-on voltage changes from −0.6 ± 0.2 V to 0.6 ± 0.4 V, field-effect mobility increases from 12 ± 1 cm2/V·s to 15 ± 1 cm2/V·s, and subthreshold-voltage swing decreases from 368 ± 50 mV/dec to 360 ± 30 mV/dec.

Modeling and Simulation of Negative Capacitance Gate on Ge FETs

In this work, a polysilicon-ferroelectric gate capacitor is proposed to be stacked on the Ge-MOSFET to simultaneously maintain the stability and the potential amplification in the sub-threshold region of a Negative Capacitance Field Effect Transistor. Hence, the non-hysteresis ID-VG characteristics with sub-60mV/dec subthreshold slope can be designed. A simple capacitance model including the effects of gate-to-source/drain overlap, interface trap states at oxide/Ge, and polysilicon/FE/metal is presented to analyze the subthreshold behavior. The optimized SS is further improved when the direct S/D overlap with floating metal of Ge-MOSFET increases. The polysilicon doping concentration causes the trade-off between subthreshold swing and hysteresis-free maximum voltage. The impact of the interface traps at the FE/poly interface on the device performance and the optimization approach are also discussed.

InP MOS capacitor and E-mode n-channel FET with ALD Al2O3-based high-k dielectric

The electrical characteristics of atomic-layer-deposited Al2O3/TiO2/Al2O3 on (NH4)2S-treated InP MOS capacitor and related MOSFET were studied. The electrical characteristics were improved from the reduction of native oxides and sulfur passivation on InP by (NH4)2S treatment. The high bandgap Al2O3 on TiO2 can reduce the thermionic emission, and the Al2O3 under TiO2 improves the interface-state density by self-cleaning. The high dielectric constant TiO2 is used to lower the equivalent oxide thickness. The leakage currents can reach 2.3 × 10−8 and 2.2 × 10−7 A/cm2 at ±2 MV/cm, respectively. The lowest interface-state density is 4.6 × 1011 cm−2 eV−1 with a low-frequency dispersion of 15 %. The fabricated enhancement-mode n-channel sulfur-treated InP MOSFET exhibits good electrical characteristics with a maximum transconductance of 146 mS/mm and effective mobility of 1760 cm2/V s. The subthreshold swing and threshold voltage are 117 mV/decade and 0.44 V, respectively.

A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping

A new δ-doped cylindrical gate silicon tunnel FET (DCG-TFET) analytical model is developed and investigated extensively, with the aim of addressing the challenges of the conventional CG-TFET. The improvement in tunneling probability of charge carriers has been achieved by inserting a δ-doping sheet in the source region which leads to high drain current as compared to CG-TFET. The effect of distance between the δ-doping sheet and source/channel interface on the current performance, sub-threshold swing (SS) and threshold voltage (Vth) has been examined. The instantaneous position of δ-doping region from the tunneling junction is optimized based on the trade-off between current ratio and SS. The present model exhibit maximum switching current ratio (IONIOFF≅1012) for an optimum distance of 2 nm without degrading SS (SS∼55 mV/decade) and Vth performance. The electrostatic behavior of the present model is obtained using the solution of Poisson’s equation in the cylindrical coordinate system. However the impact of scaling of the gate oxide thickness and cylindrical pillar diameter on drain current performance has been discussed. In future, DCG-TFET can be one of the potential successors for ultra-low-power applications because of its improved drain current and switching ratio.