Subthreshold Swing Voltage Research Articles

Influence of Doping Engineering in 1 μm Drift Layer Quasi‐Vertical Fin Field‐Effect Transistor for Achieving >139 V Breakdown Voltage

A quasi‐vertical gallium nitride (GaN) fin field effect transistor (FinFET) is designed and analyzed to assess the performance of electrical parameters. The device is deployed on a silicon carbide (SiC) substrate and analyzed using technology computer‐aided design (TCAD). The donor concentration in the critical regions is identified as a significant limiting factor for FinFET electrical properties. Hence, the influence of channel and drift layer doping concentrations (Nd) on performance characteristics is investigated in this work. The electrical characteristics such as threshold voltage, ION/IOFF ratio, subthreshold swing (SS), specific ON‐resistance, and breakdown voltage (VBV) are evaluated for various doping profiles. The doping profile with channel and drift layer concentration of 4 × 1015 cm−3 for a 300 nm fin width and 1 μm thick drift layer exhibits normally OFF behavior with a threshold voltage (Vt) of 1.5 V. It also demonstrates a VBV of 139 V. The corresponding doping profile reveals a low SS of 61 mV dec−1, which is comparable to other similar power devices. This demonstrates the significant potential of the device for medium‐power switching applications.

Investigation on palladium gate electrode-based SOI junctionless FET for hydrogen gas sensing

This study provides a comprehensive investigation on palladium (Pd) gate electrode-based silicon on insulator (SOI) junctionless field-effect transistor (JLFET) for hydrogen gas (H2) sensing (Pd–SOI-JLFET). The device has a gate dielectric stack consisting of silicon dioxide (SiO2) and hafnium dioxide (HfO2). An extensive analysis was conducted to detect and identify the presence of hydrogen gas by examining several electrical characteristics such as drain current (IDS), transconductance (gm), output conductance (gd), energy band diagram (E), gate-to-source capacitance (CGS), and surface potential (Φs). Furthermore, a comprehensive investigation was conducted to examine the impact of the presence of H2 gas and variations in temperature on important parameters associated with the short channel effects (SCEs) including off-state current (IOFF), on-state current (ION), subthreshold swing (SS) and threshold voltage (Vth). In addition, the sensitivity analysis of the off-state current (IOFF) by considering process variation effect has been done. Sensitivity is also calculated at various temperatures for the detection of hydrogen gas molecule. At the temperature of 300K, the sensitivity values were obtained as 1.50083, 3.21754, 27.71483, 152.39617 and 2052.8 for pressure values 10−14 Torr, 10−13 Torr, 10−12 Torr, 10−11 Torr and 10−10 Torr, respectively. This analysis provides a thorough examination of the performance and efficacy of the Pd–SOI-JLFET hydrogen gas sensor highlighting its potential for a wide range of hydrogen sensing applications.

Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

This work investigates the impact of electron mobility variations on short channel effects (SCEs) in different semiconductor materials using FinFETs. Using PADRE simulator, the work examines Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) FinFETs, analyzing performance metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold Voltage roll-off. The result shows that GaN-FinFET exhibits lowest subthreshold swing of 63 mV/dec at electron mobility of 10000 cm2/Vs, and threshold voltage of 0.44V at electron mobility of 10000 cm2/Vs, while Si-FinFET exhibits lowest DIBL of 3 mV/V at (4000-10000) cm2/Vs. This finding contributes to advancing the understanding of short channel effects in nanoscale FinFETs and provides valuable insights for optimizing device performance in future semiconductor technologies.

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

This study aims to enhance the efficiency of the Double Gate-Junctionless-Tunnel Field Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs-based Single Material and Tri-Material (SM and TM) configurations.In order to overcome the drawbacks of present TFET architectures, such as their limited ability to drive current and their ambipolar behaviour, and to enhance the on-state current, To execute our suggested SM-TM-DG-JL-TFET configuration. The TM structure exhibits a greater on-state current (I on ) and a lower SubthersholdSwing (SS) in comparison to SM structures. This study quantifies the Unit-gain-current-cut-off-frequency (f t ) and Maximum oscillation frequency fmax by manipulating geometric parameters such as gate length(l g ), gate-oxide thickness, and Channel thickness. The TM structure exhibits a significantly greater on-state current (I on ) of 14 × 10−3 A. Compared to SM structures, while simultaneously reducing the off-state current (I off ), subthreshold swing (SS), and threshold voltage (V t ). TM structures exhibit higher values of f t and fmax in DG-JL-TFET due to their enhanced output conductance compared to SM structures. The device exhibits potential for future low-power-RF applications due to its significant values of f t and fmax .

Investigation on Contact Properties of 2D van der Waals Semimetallic 1T-TiS2/MoS2 Heterojunctions.

Two-dimensional transition metal dichalcogenides (2D TMDCs) are considered promising alternatives to Si as channel materials because of the possibility of retaining their superior electronic transport properties even at atomic body thicknesses. However, the realization of high-performance 2D TMDC field-effect transistors remains a challenge owing to Fermi-level pinning (FLP) caused by gap states and the inherent high Schottky barrier height (SBH) within the metal contact and channel layer. This study demonstrates that high-quality van der Waals (vdW) heterojunction-based contacts can be formed by depositing semimetallic TiS2 onto monolayer (ML) MoS2. After confirming the successful formation of a TiS2/ML MoS2 heterojunction, the contact properties of vdW semimetal TiS2 were thoroughly investigated. With clean interfaces of the TiS2/ML MoS2 heterojunctions, atomic-layer-deposited TiS2 can induce gap-state saturation and suppress FLP. Consequently, compared with conventional evaporated metal electrodes, the TiS2/ML MoS2 heterojunctions exhibit a lower SBH of 8.54 meV and better contact properties. This, in turn, substantially improves the overall performance of the device, including its on-current, subthreshold swing, and threshold voltage. Furthermore, we believe that our proposed strategy for vdW-based contact formation will contribute to the development of 2D materials used in next-generation electronics.

Examining the design characteristics of a dual-material gate all-around tunnel FET for use in biosensing applications

Abstract An inventive analytical model for a dual material gate-all-around tunnel FET with possible applications in biosensors is described in this study. The semiconductor device considered in this study has a gate-all-around configuration built with two distinct materials. Short-channel effects are avoided with the help of the surrounding gate to achieve flexibility. A breakthrough dual-material design with a nanocavity has been developed to render it viable for biosensing applications. To figure out Poisson’s equation and to derive its surface potential, the Finite Differentiation Method is used in this work. The electric field, subthreshold swing, drain current, and threshold voltage of the suggested structure are then determined using this potential. Furthermore, the device’s biosensor sensitivity is examined and the results are verified by two-dimensional TCAD simulations.

Carbon nanotube network film-based field-effect transistor interface state optimization by ambient air annealing

Carbon nanotube field-effect transistors (CNTFETs) have been considered a strong candidate for post-Si era electronics due to the virtues of higher speed, lower power consumption, and multiple functionalities. The interface analysis based on the top gate structure has made little progress and lacks a reliable charge trap characterization model suitable for carbon tube devices. Quantitative extraction and analysis of the interface state are crucial for the integration of top-gate devices. Herein, a 5 nm thick Y2O3 thin film was selected as the gate dielectric layer in the top-gate CNTFETs device, and a post-annealing process in air ambience was utilized to optimize the Y2O3-CNT interface. A series of device performance evaluation results indicated that the post-annealing process in air ambience can effectively improve the on-state current and reduce the threshold voltage and subthreshold swing of the device, which are derived from diffusion of oxygen atom in the Y2O3 layer and optimization of the interface of Y2O3-CNT. Specifically, the maximum mobility, subthreshold swing, and threshold voltage are calculated to be 29 cm2/V s, 103 mV/dec, and −0.1 V, respectively, and the interface state density is reduced from 2.68 × 1012 to 1.51 × 1012 cm−2 in the gate insulator. These results not only are important to understand the dielectric impact on CNTFET devices but also are useful for future materials’ development and device optimization for high-performance CNT-based electronics.

The impact of charges at the dielectric/channel interface on performance degradation in negative capacitance ferroelectric FETs

In this study, the impact of interfacial charges including fixed charges and acceptor-type traps between the dielectric and the channel in negative capacitance ferroelectric FETs (FeFETs) is investigated by simulation based on the Landau–Khalatnikov model. The results reveal the separate impact of the fixed charges and acceptor-type traps on device performance degradation, respectively, including the subthreshold swing (SS), switching current (I on and I off) and threshold voltage (V T). On this basis, the combined impact of interfacial charges with the fixed charges and acceptor-type traps co-existing equally is further explored. Our findings indicate that the fixed charges play a key role in the V T and I off, while the acceptor-type traps predominate in the SS and I on. This study helps to understand the degradation mechanism of FeFETs and extend the device end-of-lifetime.

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS2 in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS2 MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS2 FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (ID vs. VGS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage.

Low-temperature crystallization of indium oxide thin films with a photoactivable additive

In this study, we report a simple route to the low-temperature crystallization of solution-processed indium oxide thin films by introducing ammonium nitrate in the sol–gel metal oxide precursor solution as photoactivable additive and applying deep ultraviolet (DUV) irradiation onto the as-spun oxide films in an inert atmosphere. Thermal and structural analyses revealed that the initial temperatures for condensation and crystallization were reduced down to 130 and 200 °C, respectively, by the in situ generation of reactive chemical species enabled by DUV-assisted nitrate photolysis. Furthermore, transmission electron microscopy confirmed that the degree of indium oxide film crystallinity was gradually enhanced as the amount of nitrate in the precursor solution was increased. Finally, electrical characterizations showed that carrier mobility, threshold voltage, subthreshold swing, and threshold voltage shift under the positive bias stress of sol–gel indium oxide thin-film transistors were improved from 0.21 to 5.03 cm2/V s, from 4.18 to 1.64 V, from 1.33 to 0.72 V/dec, and from 6.44 to 4.04 V, respectively, by combining ammonium nitrate and DUV photoactivation.

A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation

In this manuscript, a dual-drain Vertical Tunnel FET structure is proposed and investigated for the first time. The simulation outcomes clearly manifest that reduction in channel thickness, which has inadequate impact on the tunneling region, significantly improves numerous DC parameters of the proposed device including subthreshold swing, on-state current and current-switching ratio by enhancing the band-to-band tunneling of the charge carriers at source/channel interface caused by enlarged electric field. In order to make the proposed device suitable for low power applications, dielectric material is incorporated in between two drain/channel interfaces to reduce the subthreshold leakage current. A detailed investigation is carried out to determine the influence of varying device footprints on various electrical parameters and accordingly, the optimized device performance is achieved. TCAD-based simulation results reveal that a considerably low subthreshold swing of 18 mV decade−1 along with a high current-switching ratio of can be achieved with optimum geometric dimension of design parameters i.e., gate-oxide, source and channel. Further, the performance of the proposed device is compared with various existing TFET structures and found to be superior in terms of current switching ratio, average subthreshold swing and turn-on voltage. The probable fabrication process flow is also discussed for the proposed device and based on the proper benchmarking, it is revealed that improvement in the parameters like low-output voltage, peak overshoot and rise time defining the switching characteristics of an inverter makes the proposed device more suitable for digital circuit-based applications.

Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters

In this paper, a novel structure of gate-all-around vertical TFET (GAA-VTFET) is proposed and investigated for the first time with the help of 3D TCAD simulator. It is found that GAA-VTFET offers much improvement in various DC parameters like ION, IOFF, subthreshold swing (SSAVG), and turn-on voltage (VT) as compared with the conventional GAA-TFET. As the tunneling direction of charge carriers is in parallel to the gate electric field, channel thickness in GAA-VTFET is rigorously reduced without compromising with the tunneling area and thus, improving the tunneling rate at source/channel interface during ON-state. Further, subthreshold leakage of the charge carriers is significantly reduced due to deployment of a dielectric layer beneath channel/drain interface extending up to source region. The impact of variation in geometric dimensions is also analysed to obtain the optimum performance of the proposed device. The current-switching ratio (ION/IOFF) is observed to be in order of ∼1013 while SSAVG of 56 mV decade−1 is achieved in the proposed device. Moreover, analog/RF parameters are also analysed in this work and it is noticed that an improved cut-off frequency of 593 GHz can be achieved due to reduced parasitic capacitances along with improved transconductance in GAA-VTFET. Next, the proper benchmarking reveals that GAA-VTFET offers better ION/IOFF, VT, and SSAVG as compared with the similar devices. Finally, based on the transient analysis of inverter circuit, the proposed GAA-VTFET is found to be more suitable for digital applications as it offers less rise-time along with full-voltage swing.

High-Performance Indium-Gallium-Zinc-Oxide Thin-Film Transistors with Stacked Al2O3/HfO2 Dielectrics

High-performance amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) gated by Al2O3/HfO2 stacked dielectric films are investigated. The optimized TFTs with Al2O3 (2.0 nm)/HfO2 (13 nm) stacked gate dielectrics demonstrate the best performance, including low total trap density N t, low subthreshold swing voltage, large switching ratio I ON/OFF, high mobility μ FE, and low operating voltage, equal to 1.35 × 1012 cm−2, 88 mV/dec, 5.24 × 108, 14.2 cm2/V⋅s, and 2.0 V, respectively. Furthermore, a low-voltage-operated resistor-loaded inverter has been fabricated based on such an a-IGZO TFT, showing ideal full swing characteristics and high gain of ∼27 at 3.0 V. These results indicate a-IGZO TFTs gated by optimized Al2O3/HfO2 stacked dielectrics are of great interests for low-power, high performance, and large-area display and emerging electronics.

Impact of Al x Ga1−x barrier thickness and Al composition on electrical properties of ferroelectric HfZrO/Al2O3/AlGaN/GaN MFSHEMTs

Ferroelectric (FE) HfZrO/Al2O3 gate stack AlGaN/GaN metal-FE-semiconductor heterostructure field-effect transistors (MFSHEMTs) with varying Al x Ga1−x N barrier thickness and Al composition are investigated and compared by TCAD simulation with non-FE HfO2/Al2O3 gate stack metal–insulator–semiconductor heterostructure field-effect transistors (MISHEMTs). Results show that the decrease of the two-dimensional electron gas (2DEG) density with decreasing AlGaN barrier thickness is more effectively suppressed in MFSHEMTs than that in MISHEMTs due to the enhanced FE polarization switching efficiency. The electrical characteristics of MFSHEMTs, including transconductance, subthreshold swing, and on-state current, effectively improve with decreasing AlGaN thickness in MFSHEMTs. High Al composition in AlGaN barrier layers that are under 3-nm thickness plays a great role in enhancing the 2DEG density and FE polarization in MFSHEMTs, improving the transconductance and the on-state current. The subthreshold swing and threshold voltage can be reduced by decreasing the AlGaN thickness and Al composition in MFSHEMTs, affording favorable conditions for further enhancing the device.

Plasma-enhanced atomic-layer-deposited indium oxide thin film using a DMION precursor within a wide process window

In this study, we developed a new liquid indium precursor, dimethyl[N-(tert-butyl)-2-methoxy-2-methylpropan-1-amine] indium (DMION), to deposit indium oxide films using the plasma-enhanced atomic layer deposition (PEALD) method. The indium oxide films were deposited using DMION and Ar/O2 plasma as the precursor and reactant, respectively, with relatively high growth per cycle (GPC, ∼1.2 Å/cycle) within a wide atomic layer deposition (ALD) window (35–300 °C). Impurities such as carbon and nitrogen were not detected regardless of the deposition temperature. The crystallinity of the films had a bixbyite cubic structure within the ALD window and facets could be controlled by deposition temperature modulation; (400) facets were dominant at low deposition temperatures (35 and 100 °C), whereas (222) facets were dominant at high deposition temperatures (200 and 300 °C). The dominant facets and orientations of the indium oxide crystal were maintained until 400 °C in the post-annealing process. The thin-film transistors (TFTs) using indium oxide deposited at 200 °C exhibited high field-effect (∼32.1 cm2/Vs) mobility with a reasonable threshold voltage (∼1.8 V) and subthreshold voltage swing (∼0.48 V/decade).

Fabrication of Ferroelectric Gate Thin‐Film Transistors with a Lanthanum‐Doped HZO Gate Insulator and Indium‐Tin‐Oxide Channel via a Solution Process

In recent years, lanthanum‐doped hafnium–zirconium dioxide (La‐HZO) has garnered attention as a material for application in ferroelectric devices; moreover, atomic layer deposition has been applied to prepare La‐HZO films with metal–ferroelectric–metal structures. This article describes the fabrication of ferroelectric La‐HZO thin films on Pt/Ti/SiO2/Si substrates via a solution process. The dependence of the electrical properties on the La concentration of La‐HZO films annealed at 800 °C in vacuum is also discussed. The film with a La concentration of 8 at% exhibits the highest remanent polarization, whereas undoped HZO exhibits paraelectric behavior. Additionally, the leakage current of La‐HZO specimens tends to be significantly lower than that of undoped HZO. Furthermore, a higher annealing temperature corresponds to better ferroelectric properties and a lower leakage current. The characterization of fabricated ferroelectric gate thin‐film transistors (FGTs) with an 8 at% La‐HZO gate insulator and indium‐tin‐oxide channel is shown to confirm typical n‐channel transistor operation, i.e., a counterclockwise hysteresis loop in the transfer curve; this is attributable to the ferroelectric nature of the La‐HZO gate insulator. The results demonstrate that the proposed FGT design offers a low subthreshold voltage swing, high on/off drain current ratio of 106, large on‐current, and large memory window.

Reliability analysis of cost-efficient CH3NH3PbI3 based dopingless tunnel FET

Electrostatically-doped TFETs (ED-TFETs) are amongst the most widely used cost-efficient steeper devices due to the use of charge-plasma technique and tunneling mechanism. However, the reliability analysis of ED-TFETs is considered an important concern for the research community. Most studies have only focused on improving the performance of ED-TFETs such as dopingless (DL)-TFET in terms of on-current (I ON), subthreshold swing (SS) and threshold voltage (V th), rather than investigating the reliability issues. In this context, the aim of our work is to investigate the reliability analysis of our previously reported methyl-ammonium lead tri-iodide materials based DL-TFET (MAPbI3-DL-TFET). The influence of interface trap charges, shallow and deep defects on the electrical and analog performance of MAPbI3-DL-TFET has been analyzed using the Silvaco ATLAS tool at room temperature. Extensive results produced show that deep-level (Gaussian) defects impact the performance of the device prominently while the tail defects affect the device performance insignificantly. The present findings showed that the donor/acceptor trap charges impact the device in the subthreshold region considerably, while in the superthreshold region the impact of trap charges is marginal. In our view, these results emphasize the reliability analysis of MAPbI3-DL-TFET for the very first time. We hope that our research will be useful and valuable for DL-TFET manufacturers.

High Hole Mobility Inorganic Halide Perovskite Field‐Effect Transistors with Enhanced Phase Stability and Interfacial Defect Tolerance

AbstractSo far, it has been difficult to fabricate thin‐film field‐effect transistors (TFTs) based on inorganic halide perovskites (IHPs) due to their phase‐instability and uncontrollable trap density. Here, the bottom‐gate bottom‐contact structured p‐type TFTs are presented using the optimized IHP in the active layer. The stable cubic‐CsPbI3 phase is successfully synthesized by doping bismuth iodide and reduced defect densities by adding potassium bromide. The IHP TFTs based on the tailored cubic‐CsPbI3 show high hole mobility of ≈10 cm2 V−1 s−1, an on‐off current ratio of 103, and a low subthreshold swing voltage of 0.43 V dec−1. In addition, the operational stability of the fabricated device is demonstrated through the bias stress test. This study suggests that one of the key factors for fabricating an ideal p‐type IHP transistor is managing charge transport properties in the IHP layer through defect engineering.

Photo-induced Reactive Oxygen Species Activation for Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistors Using Sodium Hypochlorite.

We proposed a novel material named sodium hypochlorite (NaClO) solution as a source of activation for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). We reduced the activation temperature from 300 to 150 °C using NaClO solution (concentration: 50%) and obtained satisfactory electrical characteristics of a-IGZO TFTs. The field-effect mobility, threshold voltage, on/off ratio, subthreshold swing, and threshold voltage (Vth) shift under negative bias illumination stress (VG = -20 V and VD = 10.1 V for 10,000 s) of NaClO (50%)-activated a-IGZO TFTs were 10.41 cm2/V·s, 1.51 V, 2.78 × 108, 0.37 V/dec, and -5.43 V, respectively. Also, the Vth shifts of the NaClO (50%)-activated a-IGZO TFTs (150 °C) under the positive bias stress test decreased from 5.01 to 1.87 V (VG = 20 V and VD = 10.1 V for 10,000 s) compared with that of only-annealed (300 °C) a-IGZO TFTs. Also, the mechanism of NaClO activation for a-IGZO TFTs is clarified through photo-assisted oxygen radical (POR) and heat-driven oxygen radical (HOR) effects. The POR and HOR effects generated the reactive oxygen species (ROS) from NaClO solution (50%), which activated a-IGZO TFTs at a low temperature (150 °C). When the NaClO solution (50%) was exposed to external energy, it generated ROS such as hydroxyl radicals (OH•), hydroperoxyl radicals (HO2•), and oxygen radicals (O•), which promoted the formation of strong metal-oxide bonds in a-IGZO TFTs. Furthermore, NaClO solution (50%) was applied to a-IGZO TFTs on a flexible polyimide substrate and electrohydrodynamic printing process for selective deposition.

Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET)

This paper reports the performance of an epitaxial layer (ETL) based gate modulated (GM-TFET) through 3D Technology Computer Aided Design (TCAD) simulations. The architecture utilizes effects of both vertical tunneling and lateral tunneling phenomena to improve the device performance. Attributes of the ETL, its thickness (tepi) and doping concentration (Nepi) are varied and their impact on device electrical parameters such as transfer characteristic, output performance, subthreshold swing (SS), and threshold voltage (VT) is highlighted. It is observed that both tepi and Nepi significantly influence the different electrical parameters of the ETL based TFET architecture.