Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters

Abstract

In this paper, a novel structure of gate-all-around vertical TFET (GAA-VTFET) is proposed and investigated for the first time with the help of 3D TCAD simulator. It is found that GAA-VTFET offers much improvement in various DC parameters like ION, IOFF, subthreshold swing (SSAVG), and turn-on voltage (VT) as compared with the conventional GAA-TFET. As the tunneling direction of charge carriers is in parallel to the gate electric field, channel thickness in GAA-VTFET is rigorously reduced without compromising with the tunneling area and thus, improving the tunneling rate at source/channel interface during ON-state. Further, subthreshold leakage of the charge carriers is significantly reduced due to deployment of a dielectric layer beneath channel/drain interface extending up to source region. The impact of variation in geometric dimensions is also analysed to obtain the optimum performance of the proposed device. The current-switching ratio (ION/IOFF) is observed to be in order of ∼1013 while SSAVG of 56 mV decade−1 is achieved in the proposed device. Moreover, analog/RF parameters are also analysed in this work and it is noticed that an improved cut-off frequency of 593 GHz can be achieved due to reduced parasitic capacitances along with improved transconductance in GAA-VTFET. Next, the proper benchmarking reveals that GAA-VTFET offers better ION/IOFF, VT, and SSAVG as compared with the similar devices. Finally, based on the transient analysis of inverter circuit, the proposed GAA-VTFET is found to be more suitable for digital applications as it offers less rise-time along with full-voltage swing.