Subthreshold Region Of Operation Research Articles

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

This research paper introduces a novel design for a hybrid-CMOS inverter using vanadium dioxide (VO2), a phase transition material. The proposed inverter exhibits a remarkably steep transition for falling logic at the output(1–0). By leveraging the insulating to metallic current density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS inverter, the designed inverter demonstrates several advantages. It achieves higher values of lower noise margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for designing inverters at lower drain voltages, especially in devices operating at lower technology nodes. Furthermore, the hybrid-CMOS inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower noise margin and reduced leakage current values.

Negative Capacitance Dual-Gated ISFETs as Ultra-Sensitive pH Sensors.

Ion-sensitive field-effect transistors (ISFETs) are promising candidates for next-generation pH sensors, enabling highly sensitive and label-free biomolecular and chemical detection. Emerging FETs based on the negative capacitance (NC) effect offer steep-subthreshold switching and higher drive current simply by integrating a ferroelectric (FE) material into the gate stack. Here, we propose a novel NC dual-gated ISFET (NC-DG-ISFET)-based pH sensor, with FE layers integrated into both the top and the bottom gate stacks. The current and voltage sensitivities of the proposed device are extracted from its transfer characteristics, obtained by combining the numerical solutions of the one-dimensional (1D) Landau-Khalatnikov (L-K) equation with three-dimensional (3D) technology computer-aided design (TCAD) simulations. Results show that the NC-DG-ISFET can surpass the sensitivity of some of the state-of-the-art DG-ISFET pH sensors. The inclusion of the FE layers into the gate stacks of a baseline DG-ISFET leads to 51% reduction in subthreshold swing (SS), causing a 5× increase in current sensitivity (SI) in the subthreshold region of operation and a 2× increase in voltage sensitivity (SV). The influence of channel thickness and channel length on the sensor performance is also invesitgated. The findings presented here provide a new pathway to leverage the steep-switching behavior of NCFETs for the next generation of highly sensitive and label-free DG-ISFET pH sensors.

Investigation on the interface trap characteristics in a p-channel GaN MOSFET through temperature-dependent subthreshold slope analysis

In this paper, a simple method based on subthreshold slopes was proposed to investigate the interface trap characteristics in a p-channel GaN MOSFET with a p-GaN/AlGaN/GaN structure on Si. The energy distribution of the interface trap density has been extracted from the analysis of the transfer characteristics in the subthreshold region of operation. The interface trap densities and respective energy distribution at both room temperature and 150 °C were also calculated from the ac conductance measurements at corresponding applied biases. Both characterization methods show similar results of trap densities and energy levels.

AlGaN/AlN/GaN SG-HEMT as pH detector: A simulation study

Unlike other FETs where a sub-threshold regime is preferred for pH detection where power is a constraint, here both subthreshold and saturation region of operation can be used for sensing. In the saturation region, a large change in drain current shift is obtained compared to the sub-threshold region which leads to enhanced sensitivity. Similarly, sub-threshold parameters like transconductance (gm), current ratio gm/IDS, threshold voltage (Vth) also can be applied as effective sensing metrics for biochemical sensing. The HEMT sensor design with AlN interlayer’s in the epitaxial design and thin Al2O3 gate oxide layer enhances the overall performance of the device and gm sensitivity. Using TCAD simulation an investigation is done on the applicability of different sensing metrics through the development of a charge-controlled model for the sensitivity analysis of solution gated HEMT (SGHEMT) for pH-sensing. The simulation results indicate the high potential of the device for pH detection.

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

Subthreshold Region based Linear Feedback Shift Register

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis

ABSTRACT In VLSI integrated circuits, devices and interconnects are the steady pillars for designing and realization of the entire system. Demand for ultra-low power requirements has become very essential in today’s modern portable and miniaturized electronic gadgets. The subthreshold modelling and its utility for miniaturized gadgets and low power applications have increased tremendously in recent days. Operating devices and interconnects in the subthreshold region profoundly enhance the performance of the system. In this paper, contemporary subthreshold modelling has been energetically taken. The novel modelling of subthreshold for device and on-chip interconnects has been first time presented using the numerical method based finite-difference time-domain (FDTD) technique. The advanced graphene on-chip interconnects have been considered for the performance analysis. The technology node considered is 22 nm. It is analysed that graphene-based MLGNR interconnects possess better performance over copper interconnects. It is also seen that subthreshold region of operation leads to significantly lower power dissipation than in linear region. Power saving with the subthreshold region of operation in case of conventional copper and advanced graphene interconnects is nearly 22% and 26% respectively. The veracious proposed FDTD modelling for the subthreshold region is highly accurate with respect to SPICE simulation results. The average percentage error for transient simulation is less than 2%.

Subthreshold Operation of Organic Electrochemical Transistors for Biosignal Amplification.

With a host of new materials being investigated as active layers in organic electrochemical transistors (OECTs), several advantageous characteristics can be utilized to improve transduction and circuit level performance for biosensing applications. Here, the subthreshold region of operation of one recently reported high performing OECT material, poly(2‐(3,3′‐bis(2‐(2‐(2‐methoxyethoxy)ethoxy)ethoxy)‐[2,2′‐bithiophen]‐5‐yl)thieno[3,2‐b]thiophene), p(g2T‐TT) is investigated. The material's high subthreshold slope (SS) is exploited for high voltage gain and low power consumption. An ≈5× improvement in voltage gain (A V) for devices engineered for equal output current and 370× lower power consumption in the subthreshold region, in comparison to operation in the higher transconductance (g m), superthreshold region usually reported in the literature, are reported. Electrophysiological sensing is demonstrated using the subthreshold regime of p(g2T‐TT) devices and it is suggested that operation in this regime enables low power, enhanced sensing for a broad range of bioelectronic applications. Finally, the accessibility of the subthreshold regime of p(g2T‐TT) is evaluated in comparison with the prototypical poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), and the role of material design in achieving favorable properties for subthreshold operation is discussed.

Impact of inelastic phonon scattering in the OFF state of Tunnel-field-effect transistors

We study the impact of electron---phonon interaction on the subthreshold operation region of Tunnel-FETs by means of full-quantum simulations. Our approach is based on the nonequilibrium Green's function method, where acoustic and optical phonon scatterings are taken into account through the self-consistent Born approximation. Two device architectures are analyzed: InAs nanowire longitudinal Tunnel-FETs, and 2D vertical Tunnel-FETs based on either an GaSb/AlSb/InAs heterostructure or a MoS$$_2$$2/WTe$$_2$$2 van der Waals heterojunction. In InAs nanowire Tunnel-FETs with interface traps, electron---phonon interaction deteriorates the subthreshold swing by allowing trap-assisted tunneling at energies higher than the valence-band edge in the source. In vertical heterojunction Tunnel-FETs, optical phonon scattering increases the OFF current by inducing inelastic transition in the overlap region even in the absence of traps.

Performance improvement of poly-Si tunnel thin-film transistor by NH3 plasma treatment

In this paper, low-temperature polycrystalline silicon (poly-Si) tunnel thin-film transistors (tunnel-TFTs) are demonstrated to show excellent short-channel effects immunity due to their special current transport mechanism: inter-band tunneling. The ammonia (NH3) plasma surface treatment before the deposition of gate dielectric can significantly reduce the grain boundary trap state densities (NGB) of poly-Si channel film and the interface trap state densities (Nit) at the gate-oxide/poly-Si interface. About 27% reduction of NGB by NH3 plasma surface treatment can reduce the minimum drain current ~0.51× and improve the subthreshold slope due to the suppression of trap-assisted tunneling, which dominates the current transport in the subthreshold operation region. In addition, about 37% reduction of Nit by NH3 plasma surface treatment can significantly enhance the on-state current ~2.86× due to the increase of band bending of poly-Si channel potential, which can decrease the tunneling distance to increase the electron tunneling probability. Consequently, the performance improvement of poly-Si tunnel-TFTs by the NH3 plasma surface treatment would be helpful for the development of system-on-panel and three-dimension integrated circuits.

Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits

The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in the subthreshold region with no extra energy cost. The optimum pMOS-to-nMOS width ratio is obtained and compared through three approaches: 1) finding the maximum current-over-capacitance ratio of a biased transistor; 2) deriving an analytical expression by minimizing the delay of an inverter; and 3) simulating different CMOS logic gates in the subthreshold region. Simulation results illustrate that in the subthreshold region, the frequency attains its maximum at the optimum pMOS-to-nMOS width ratio independent of the supply voltage. Using this optimum value in designing a carry-look-ahead adder improves the propagation delay, energy consumption, and energy-delay product by up to 33%, 36%, and 57%, receptively, compared with when the conventional pMOS-to-nMOS width ratio (in the superthreshold region) is used. We verified our analytical model by performing circuit simulations in four CMOS technologies (TSMC 180 nm, IBM 130 nm, TSMC 90 nm, and ST 65 nm).

Capacitance Modeling in Dual Field-Plate Power GaN HEMT for Accurate Switching Behavior

In this paper, a surface-potential-based compact model is proposed for the capacitance of an AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure, i.e., with gate and source FPs. FP incorporation in a HEMT gives an improvement in terms of enhanced breakdown voltage, reduced gate leakage, and so on, but it affects the capacitive nature of the device, particularly by bringing into existence in a subthreshold region of operation, a feedback miller capacitance between the gate and the drain, and also a capacitance between the drain and the source, therefore, affecting switching characteristics. Here, we model the bias dependence of the terminal capacitances, wherein the expressions developed for intrinsic charges required for capacitance derivation are analytical and physics-based in nature and valid for all regions of device operation. The proposed model, implemented in Verilog-A, is in excellent agreement with the measured data for different temperatures.

Carrier transport across grain boundaries in polycrystalline silicon thin film transistors

We established a model for investigating polycrystalline silicon (poly-Si) thin film transistors (TFTs). The effect of grain boundaries (GBs) on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region, and the dominant transport mechanism of carrier across grain boundaries was subsequently determined. It is shown that the thermionic emission (TE) is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary. To a poly-Si TFT model with a 1 nm-width grain boundary, in the linear region, thermionic emission is similar to that of tunneling (TU), however, with increasing grain boundary width and number, tunneling becomes dominant.

Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region

When traditional planar Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are scaled, they lose the gate control over the channel charges because the charges are partially controlled by the drain/source depletion regions [1]. Several types of nonplanar structures with multiple-gated configuration have been proposed for providing better electrostatic control of the charges in the channel region; therefore reducing short-channel effects (SCEs) – like subthreshold slope (SS) degradation, threshold voltage roll-off (TVRO) and drain-induced barrier lowering (DIBL) [2]. However, further miniaturization of such devices becomes quite challenging because of the formation of ultra-shallow and abrupt junctions which requires novel doping and special annealing techniques. Junctionless Field Effect Transistors (JLFETs) have recently been proposed to provide a solution for this issue which typically consist of the source and drain having same doping type as the channel and the thickness of the silicon body thin enough to make the silicon body fully depleted when switched off [3]. Therefore, JLFETs need neither lateral abrupt doping, nor high thermal budget, thus making manufacturing simpler. Besides that JLFETs provide reduced SCEs, an excellent SS, a very low leakage current and high Ion/Ioff ratio compared to conventional MOSFETs [4]. A number of studies based on simulations and analytical solutions have been performed to anticipate the performance of symmetric JLFETs [5-7]. However, a complete analytical treatment for both symmetric and asymmetric double gate JLFETs is necessary to make a comparative study of their performance. In this work, we propose a physically based analytical model of 2D electrostatic potential in the subthreshold region applicable for different structures of JLFET. The schematic cross-sectional view of an n-type double gate JLFET considered in this work is shown in figure 1. The thickness of the source and drain regions are assumed to be zero for the sake of simplicity of modeling. The source and drain electrodes are shown to be present at the two side of the bulk silicon layer which is heavily doped with n-type impurity. Figure 2 shows the analytical expression of 2D electrostatic potential in the channel region of double gate JLFET. In order to obtain the equation, we analytically solve 2D Poisson’s equation in the channel region using cubic approximation with appropriate boundary conditions. This analytical solution is valid in the subthreshold region of operation for both symmetric and asymmetric double gate JLFETs with similar and dissimilar gate bias configurations. αy and βy in the equation depend on the physical parameters and position along Y-axis which are not shown in the figure. Figure 3 and 4 show the surface plot of 2D channel potential distribution for symmetric and asymmetric double gate n-channel JLFET respectively. In this work we consider symmetric structure with P+ polysilicon as both gate electrodes and asymmetric structure with P+ polysilicon and Ni metal as top and bottom gate electrodes respectively. For a fully depleted double gate JLFETs, the threshold voltage is reached when a portion of the channel is no longer depleted, such that bulk current flows through a neutral path. The threshold voltage of symmetric and asymmetric JLFETs is obtained using the 2D potential model shown in figure 2 by determining the gate voltage for which minimum channel potential along source to drain direction at a particular depth of the silicon channel along the top to bottom gate direction becomes zero. DIBL of JLFETs can be defined as the lowering in the threshold voltage due to the increase in the drain voltage. In this work DIBL is also calculated by varying Vds from 0.1V to 1V. Figure 5 and 6 exhibits the variation of TVRO and DIBL with the channel length of symmetric and asymmetric double gate JLFETs respectively. The asymmetric structure demonstrates smaller TVRO and less DIBL than the symmetric structure when the devices are shrunk into a deep-submicrometer regime. In this work we have obtained a 2D channel potential model in subthreshold region for double gate JLFETs. The analytical potential model is further used to determine TVRO and DIBL of symmetric and asymmetric JLFETS so that performance comparison of subthreshold characteristics can be made between different structures of JLFET.

Compact models and delay computation of sub-threshold interconnect circuits

Ultra-low power designs extensively exploit the sub-threshold region of operation of Complementary metal-oxide semiconductor (CMOS) circuits. Though sub-threshold circuit operation shows huge potential towards satisfying the ultra-low power requirement, increased crosstalk and delay have become serious design challenges particularly for sub-threshold interconnects. In this paper, novel analytical time-domain models governing the output voltage and crosstalk-induced delay of CMOS gates driving coupled resistive---capacitive interconnect in sub-threshold domain are presented. Subsequently, the transient analysis of simultaneously switching two and three coupled interconnects is carried out. It is demonstrated that the modeling of driver by linear resistance can lead to about 38 % average error in the estimation of propagation delay. The numerical results illustrate that the proposed model quite accurately estimates the performance of coupled on-chip interconnects. An average error of less than 7 % is observed in estimation of waveform shape and delay.

Optimization and Characterization of CMOS for Ultra Low Power Applications

Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selectingVthandTOXis much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage inION/IOFFratio for the same drive current.

ENHANCEMENT IN POWER-DELAY PRODUCT BY DRIVER AND INTERCONNECT OPTIMIZATION

To obtain higher performance with maximum devices and smaller chip size semiconductor devices are continuously shrinking. However, leakage power dissipation increases significantly with the technology scaling. Increasing demand for ultra low power devices has increased significantly since last decade and it compels advance technological solutions to fulfill power requirements of electronic appliances. As a result subthreshold operation region and different device optimization techniques attracts different researchers to achieve ultra low power design of VLSI circuits. Power supply reduction is supposed to be the main parameter to reduce power reduction. However, deep subthreshold region offers speed penalty degrading the overall performance of a device which suggests the need for optimizing device parameters. This paper analyzes the driver and interconnects performance by changing threshold voltage (Vth) and oxide thickness (Tox) in subthreshold region. Further, it also compares the optimized driver performance and DTMOS driver performance at 0.4 V. Moreover, a large amount of gain in performance was observed when optimized interconnect is used with the optimized driver. Result shows that performance of a circuit enhances if the optimized driver is used compared to DTMOS driver.

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

The need for power-efficient memories that are capable of operating at low supply voltages has led to the development of several alternative bit cell topologies. The majority of the proposed designs are based on the 6T bit cell with the addition of devices and/or peripheral techniques aimed at reducing leakage and enabling read and write functionality at lower operating voltages. In this brief, we propose a reduced transistor count bit cell that is fully functional in the sub-threshold (ST) region of operation. This asymmetric 5T bit cell is operated through a single-ended read and differential write scheme, with an option for operation as a two-port cell with single-ended write. The bit cell's operating scheme provides a non intrusive read operation and improved write margins for robust functionality. In addition, the circuit's asymmetric characteristic provides a low-leakage state with an additional 5X static power improvement over the reduction inherently achieved through voltage lowering. The proposed bit cell was designed and simulated in a 40-nm commercial CMOS process and is shown to be fully operational at ST voltages as low as 400 mV under global and local process variations. At this supply voltage, a 21X static power reduction is achieved, as compared to the industry-standard 6T bit cell, operated at its minimum supply voltage.

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.

Robustness Comparison of Emerging Devices for Portable Applications

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations.