Robustness Comparison of Emerging Devices for Portable Applications

S D Pable,Mohd Hasan,A K Kureshi,Mohd Ajmal Kafeel

doi:10.1155/2012/242459

Abstract

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations.

Highlights

ultralow power (ULP) applications like pacemakers, hearing aids, body-based sensor networks, wireless sensor networks, and many other biomedical systems are bounded by ULP budget rather than the higher performance
The parasitic off-state leakage current of a MOSFET is utilized as the switching current for designing ULP circuits
While designing low-power circuits, importance is given to operate the device at minimum energy delay point (EDP) instead of minimum energy point (MEP)

Summary

Introduction

ULP applications like pacemakers, hearing aids, body-based sensor networks, wireless sensor networks, and many other biomedical systems are bounded by ULP budget rather than the higher performance. The VDD is reduced to the threshold voltage (Vth) of the MOSFET Under this condition, the power consumption is significantly reduced up to milli Watt range but the speed of such circuits degrades substantially. The power consumption is significantly reduced up to milli Watt range but the speed of such circuits degrades substantially This region of operation of a Si-MOSFET is popularly known as a subthreshold region. While designing low-power circuits, importance is given to operate the device at minimum energy delay point (EDP) instead of minimum energy point (MEP)

Device Design Metric under Subthreshold Conditions

Structure of DG FinFET Device

Optimisation of CNFET under Subthreshold Conditions

Performance Comparison of Emerging Devices under Subthreshold Conditions

Findings

Conclusions