Subthreshold Regime Research Articles

Low-Frequency Noise Characteristics in Multilayer MoTe2 FETs With Hydrophobic Amorphous Fluoropolymers

This letter investigates the low-frequency noise (LFN) properties of the multilayer MoTe2 field-effect transistors (FETs) before and after hydrophobic amorphous polymer (CYTOP) encapsulation in the subthreshold and linear regimes. The noise spectrum density of drain current (SID) shows that the LFN in the multilayer MoTe2 FETs nicely fits to a 1/ $f^{\gamma }$ power law with $\gamma \sim \textsf {1}$ in the frequency range of 10–200 Hz. From the dependence of SID on the drain current, carrier number fluctuation ( $\Delta n$ ) is considered as a dominant LFN mechanism from all operation regimes in the multilayer MoTe2 FETs. Extracted trap density (Nt) based on the McWhorter model in this letter was reduced at least more than one order level compared with the multilayer MoTe2 FETs without CYTOP passivation.

Employing Drain-Bias Dependent Electrical Characteristics of Poly-Si TFTs to Improve Gray Level Control in Low Power AMOLED Displays

With development of high efficiency organic light emitting diodes (OLEDs), and high mobility polycrystalline silicon (poly-Si) thin-film transistors (TFTs), low power and high resolution active matrix OLED (AMOLED) displays are becoming popular for mobile applications. However, they suffer from poor control of lower gray levels, with the driving TFT being operated in the subthreshold regime. In this paper, with help of non-ideal drain-bias dependent electrical characteristics of poly-Si TFTs, operation of the driving TFT can be moved out from the subthreshold regime to allow better control of the gray levels. As a result, a dynamic voltage scaling (DVS) method is developed, and shown to be able to improve the luminous uniformity for better image quality, while effectively reducing the static power consumption.

Modeling Short-Channel Effects in Core–Shell Junctionless MOSFET

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness ( ${T}_{\textsf {core}}$ ), shell doping ( ${N}_{\textsf {d}}$ ), gate length ( ${L}_{\textsf {g}}$ ), and gate ( ${V}_{\textsf {gs}}$ ) and drain ( ${V}_{\textsf {ds}}$ ) biases in subthreshold regime. The threshold voltage ( ${V}_{\textsf {th}}$ ), drain-induced barrier lowering and subthreshold swing ( ${S}$ ), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications.

High performance indium oxide nanoribbon FETs: mitigating devices signal variation from batch fabrication.

Nanostructured field effect transistor (FET) based sensors have emerged as a powerful bioanalytical technology. However, performance variations across multiple devices and between fabrication batches inevitably exist and present a significant challenge holding back the translation of this cutting-edge technology. We report an optimized and cost-effective fabrication process for high-performance indium oxide nanoribbon FET with a steep subthreshold swing of 80 mV per decade. Through systematic electrical characterizations of 57 indium oxide nanoribbon FETs from different batches, we demonstrate an optimal operation point within the subthreshold regime that mitigates the issue of device-to-device performance variation. A non-linear pH sensing of the fabricated indium oxide nanoribbon FETs is also presented.

Proposal and Analysis of Mixed CNT Bundle for Sub-Threshold Interconnects

We report, for the first time, mixed CNT bundle (MCB) as prospective interconnect in the sub-threshold regime. MCBs with spatial and random distribution of single- and multi-walled CNTs of non-identical diameters are proposed. An analytic model to compute sub-threshold crosstalk delay in coupled MCB interconnects is introduced. Using the proposed model, the impact of interconnect length on the delay performance and transfer gain for coupled MCB interconnects is studied. It is observed that sub-threshold MCB interconnects demonstrate improved crosstalk delay and higher cutoff frequency in comparison to the MWCNT and copper counterparts. The proposed model efficiently computes the performance of sub-threshold MCB interconnect system with less than 3% average error.

An Analytical Subthreshold Swing Model for fully-depleted MOSFETs with vertical Gaussian profile fabricated on modified silicon-on-insulator wafers

The objective of this study is to present an analytical subthreshold swing model for fully-depleted metal-oxide semiconductor field-effect transistors (MOSFETs) with vertical Gaussian profile fabricated on modified Silicon-on-Insulator (SOI) wafers. Commercial SOI wafers are radiation hardened by Si+ implantation which creates interface traps at buried SiO2/Si interface. Considering that channel potential is affected by non-uniform doping profile combined with process- and radiation-induced traps, the model is derived based on effective conduction path effect. The proposed model is validated by comparing analytical results with numerical simulation data obtained by using commercially available Sentaurus technology computer-aided design. The model agrees well with experimental extractions of irradiated nMOSFETs. This model is believed to be able to provide better physical insight and understanding of total dose irradiated modified SOI MOSFET devices operating in subthreshold regime.

Coulomb scattering mechanism transition in 2D layered MoTe2: effect of high-κ passivation and Schottky barrier height

Clean interface and low contact resistance are crucial requirements in two-dimensional (2D) materials to preserve their intrinsic carrier mobility. However, atomically thin 2D materials are sensitive to undesired Coulomb scatterers such as surface/interface adsorbates, metal-to-semiconductor Schottky barrier (SB), and ionic charges in the gate oxides, which often limits the understanding of the charge scattering mechanism in 2D electronic systems. Here, we present the effects of hafnium dioxide (HfO2) high-κ passivation and SB height on the low-frequency (LF) noise characteristics of multilayer molybdenum ditelluride (MoTe2) transistors. The passivated HfO2 passivation layer significantly suppresses the surface reaction and enhances dielectric screening effect, resulting in an excess electron n-doping, zero hysteresis, and substantial improvement in carrier mobility. After the high-κ HfO2 passivation, the obtained LF noise data appropriately demonstrates the transition of the Coulomb scattering mechanism from the SB contact to the channel, revealing the significant SB noise contribution to the 1/f noise. The substantial excess LF noise in the subthreshold regime is mainly attributed to the excess metal-to-MoTe2 SB noise and is fully eliminated at the high drain bias regime. This study provides a clear insight into the origin of electronic signal perturbation in 2D electronic systems.

Silicon Field Effect Transistor as the Nonlinear Detector for Terahertz Autocorellators.

We demonstrate that the rectifying field effect transistor, biased to the subthreshold regime, in a large signal regime exhibits a super-linear response to the incident terahertz (THz) power. This phenomenon can be exploited in a variety of experiments which exploit a nonlinear response, such as nonlinear autocorrelation measurements, for direct assessment of intrinsic response time using a pump-probe configuration or for indirect calibration of the oscillating voltage amplitude, which is delivered to the device. For these purposes, we employ a broadband bow-tie antenna coupled Si CMOS field-effect-transistor-based THz detector (TeraFET) in a nonlinear autocorrelation experiment performed with picoseconds-scale pulsed THz radiation. We have found that, in a wide range of gate bias (above the threshold voltage mV), the detected signal follows linearly to the emitted THz power. For gate bias below the threshold voltage (at 350 mV and below), the detected signal increases in a super-linear manner. A combination of these response regimes allows for performing nonlinear autocorrelation measurements with a single device and avoiding cryogenic cooling.

Correcting coherent errors with surface codes

Surface codes are building blocks of quantum computing platforms based on 2D arrays of qubits responsible for detecting and correcting errors. The error suppression achieved by the surface code is usually estimated by simulating toy noise models describing random Pauli errors. However, Pauli noise models fail to capture coherent processes such as systematic unitary errors caused by imperfect control pulses. Here we report the first large-scale simulation of quantum error correction protocols based on the surface code in the presence of coherent noise. We observe that the standard Pauli approximation provides an accurate estimate of the error threshold but underestimates the logical error rate in the sub-threshold regime. We find that for large code size the logical-level noise is well approximated by random Pauli errors even though the physical-level noise is coherent. Our work demonstrates that coherent effects do not significantly change the error correcting threshold of surface codes. This gives more confidence in the viability of the fault-tolerance architecture pursued by several experimental groups.

Ultralow Power Dual-Gated Subthreshold Oxide Neuristors: An Enabler for Higher Order Neuronal Temporal Correlations.

Inspired by neural computing, the pursuit of ultralow power neuromorphic architectures with highly distributed memory and parallel processing capability has recently gained more traction. However, emulation of biological signal processing via artificial neuromorphic architectures does not exploit the immense interplay between local activities and global neuromodulations observed in biological neural networks and hence are unable to mimic complex biologically plausible adaptive functions like heterosynaptic plasticity and homeostasis. Here, we demonstrate emulation of complex neuronal behaviors like heterosynaptic plasticity, homeostasis, association, correlation, and coincidence in a single neuristor via a dual-gated architecture. This multiple gating approach allows one gate to capture the effect of local activity correlations and the second gate to represent global neuromodulations, allowing additional modulations which augment their plasticity, enabling higher order temporal correlations at a unitary level. Moreover, the dual-gate operation extends the available dynamic range of synaptic conductance while maintaining symmetry in the weight-update operation, expanding the number of accessible memory states. Finally, operating neuristors in the subthreshold regime enable synaptic weight changes with high gain while maintaining ultralow power consumption of the order of femto-Joules.

Analytical Modeling of Gate-Stack DG-MOSFET in Subthreshold Regime by Green’s Function Approach

An accurate analytical model of the gate-stack symmetric double-gate (DG) MOSFET using Green's function approach is developed in this brief. An exact analytical solution to 2-D Poisson's equation is derived in the subthreshold regime of operation, considering 2-D mixed boundary conditions and multizone techniques. It is observed that the Green's function approach of solving 2-D Poisson's equation in both oxides (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox1</sub> and t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox2</sub> ) and silicon region can accurately predict channel potential and subthreshold current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) of gate-stack DG-MOSFET. We further extend our model to mitigate the fringe-induced barrier lowering (FIBL) effect in the gate-stack device, by optimizing the interfacial layer thickness. It is observed that selection of interfacial SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer as ~0.75 times of equivalent oxide thickness is necessary to completely mitigate the FIB' effect of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate-stack DG-MOSFET.

Characterization and Compact Modeling of Self-Aligned Short-Channel Organic Transistors

In this paper, we present the characterization and modeling of downscaled flexible organic thin-film transistors fabricated by photolithography and self-alignment of the source and drain contacts to the gate. A SPICE model based on the unified model and extraction method for thin-film transistors (TFTs) is tailored with high accuracy for the subthreshold regime in order to include the channel length dependence of two semiempirical parameters, viz., the effective mobility and the onset voltage. In addition, we demonstrate the modeling of the hump effect, a phenomenon often present in TFTs fabricated by lithographic methods.

Ultra low power DG FinFET based voltage controlled oscillator circuits

ABSTRACTVoltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.

DC Gate Leakage Current Model Accounting for Trapping Effects in AlGaN/GaN HEMTs

A DC leakage current model accounting for trapping effects under the gate of AlGaN/GaN HEMTs on silicon has been developed. Based on TCAD numerical simulations (with Sentaurus Device), non-local tunneling under the Schottky gate is necessary to reproduce the measured transfer characteristics in a subthreshold regime. Once the trap concentration and distribution are determined in the device, the resulting gate leakage current is modeled making use of Verilog-A, for typical operation regimes.

Modeling Short-Channel Effects in Asymmetric Junctionless MOSFETs With Underlap

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications.

Impact of dislocations on DLTS spectra and degradation of InGaN-based laser diodes

The aim of this paper is to illustrate the dependence of DLTS characteristics and degradation of InGaN-based laser diodes (LDs) on the density of dislocations. Three groups of multi-quantum well LDs with different dislocation densities were submitted to constant current stress, at room temperature: the analysis is based on combined electrical-optical measurements and Deep-Level Transient Spectroscopy (DLTS) investigation was made before and after stress. DLTS results show the presence of a hole trap in all the samples, whose intensity is related to the dislocation density. Constant current stress induces a significant decrease in the optical power (subthreshold regime), not related exclusively to the dislocation density, and the appearance of a new deep level for electrons (point defect generated after stress).

Analysis of subthreshold SOI FinFET based two stage OTA for low power

In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by $$g_{m}/I_{D}$$ methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and $$\pm 0.5 V$$ ;respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.

Pinning of domain walls in thin ferromagnetic films

We present a quantitative investigation of magnetic domain wall pinning in thin magnets with perpendicular anisotropy. A self-consistent description exploiting the universal features of the depinning and thermally activated sub-threshold creep regimes observed in the field driven domain wall velocity, is used to determine the effective pinning parameters controlling the domain wall dynamics: the effective height of pinning barriers, the depinning threshold, and the velocity at depinning. Within this framework, the analysis of results published in the literature allows for a quantitative comparison of pinning properties for a set of magnetic materials in a wide temperature range. On the basis of scaling arguments, the microscopic parameters controlling the pinning: the correlation length of pinning, the collectively pinned domain wall length (Larkin length) and the strength of pinning disorder, are estimated from the effective pinning and the micromagnetic parameters. The analysis of thermal effects reveals a crossover between different pinning length scales and strengths at low reduced temperature.

DC Compact Model for Subthreshold Operated Organic Field-Effect Transistors

To accurately describe the electrical behaviors of organic field-effect transistors (OFETs) across the whole subthreshold regime, a compact model considering both non-exponential gate-voltage-dependent diffusion current and additional drift current is developed. The two current components in the subthreshold regime are combined into one closed-form expression with a hyperbolic tangent transition function. By fitting transfer and output curves in the subthreshold regime at different bias voltages, the model is shown to be applicable to OFETs in different materials and device structures of large and small subthreshold swings. The model is further demonstrated continuity with the OFF-state and above-threshold regimes when being incorporated into a commercial SPICE simulator for circuit simulations.

Subthreshold Operation of Organic Electrochemical Transistors for Biosignal Amplification.

With a host of new materials being investigated as active layers in organic electrochemical transistors (OECTs), several advantageous characteristics can be utilized to improve transduction and circuit level performance for biosensing applications. Here, the subthreshold region of operation of one recently reported high performing OECT material, poly(2‐(3,3′‐bis(2‐(2‐(2‐methoxyethoxy)ethoxy)ethoxy)‐[2,2′‐bithiophen]‐5‐yl)thieno[3,2‐b]thiophene), p(g2T‐TT) is investigated. The material's high subthreshold slope (SS) is exploited for high voltage gain and low power consumption. An ≈5× improvement in voltage gain (A V) for devices engineered for equal output current and 370× lower power consumption in the subthreshold region, in comparison to operation in the higher transconductance (g m), superthreshold region usually reported in the literature, are reported. Electrophysiological sensing is demonstrated using the subthreshold regime of p(g2T‐TT) devices and it is suggested that operation in this regime enables low power, enhanced sensing for a broad range of bioelectronic applications. Finally, the accessibility of the subthreshold regime of p(g2T‐TT) is evaluated in comparison with the prototypical poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), and the role of material design in achieving favorable properties for subthreshold operation is discussed.