Subthreshold Characteristics Research Articles

Origin of Hole‐Trapping States in Solution‐Processed Copper(I) Thiocyanate and Defect‐Healing by I2 Doping

AbstractSolution‐processed copper(I) thiocyanate (CuSCN) typically exhibits low crystallinity with short‐range order; the defects result in a high density of trap states that limit the device's performance. Despite the extensive electronic applications of CuSCN, its defect properties are not understood in detail. Through X‐ray absorption spectroscopy, pristine CuSCN prepared from the standard diethyl sulfide‐based recipe is found to contain under‐coordinated Cu atoms, pointing to the presence of SCN− vacancies. A defect passivation strategy is introduced by adding solid I2 to the processing solution. At small concentrations, the iodine is found to exist as I− which can substitute for the missing SCN− ligand, effectively healing the defective sites and restoring the coordination around Cu. Computational study results also verify this point. Applying I2‐doped CuSCN as a p‐channel in thin‐film transistors shows that the hole mobility increases by more than five times at the optimal doping concentration of 0.5 mol.%. Importantly, the on/off current ratio and the subthreshold characteristics also improve as the I2 doping method leads to the defect‐healing effect while avoiding the creation of detrimental impurity states. An analysis of the capacitance‐voltage characteristics corroborates that the trap state density is reduced upon I2 addition.

Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET

Device reliability issues originating from interface traps or bias temperature instability has been of great concern in emerging devices such as negative capacitance (NC)-fin field effect transistor (FinFET), gate-all-around field-effect transistor etc. Exploration of the interface traps at the different interfaces of these three-dimensional devices is of much importance in predicting the reliability of device behavior. In the proposed analysis, for the first time, we have demonstrated the individual and the overall impact of trap densities at the various practical interfaces present in the gate and spacer stack of the ferroelectric (FE)-dielectric spacer based NC-FinFET. The trap states in the proposed device alter the polarization dynamics and improve sub-threshold characteristics especially the off-state current (I OFF), thus revealing excellent short-channel characteristics. We have further evaluated the degree of performance degradation occurring due to interface traps by means of optimized capacitance matching (FE parameters), hysteretic window, output transconductance (gds) and voltage gain (AV ). Furthermore, we have also studied the impact of trap states on the mixed-mode characteristics of the spacer-based NC-FinFET inverter design.

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

High Field-Effect Mobility and On/Off Current Ratio of p-Type ALD SnO Thin-Film Transistor

High-performance p-type thin-film transistors (TFTs) with high field-effect mobility and high on/off current ratios (Ion/Ioff) were fabricated by engineering the microstructure and surface morphology of the atomic layer-deposited (ALD) SnO channel layer. ALD SnO films grown at a deposition temperature of 225 °C showed excellent crystallinity and dense, smooth surfaces, which resulted in superior field-effect mobility of 6.13–7.24 cm2/V·s without using a high-temperature postannealing process. Optimization of the SnO channel thickness suppressed the off-state leakage current, which consequently yielded excellent TFT switching performance, with an Ion/Ioff value of 104–105. Additionally, backchannel passivation by the ALD Al2O3 film improved the subthreshold swing characteristics by reducing surface defect states. These results suggest that synergistic control of the microstructure, surface morphology, and thickness of ALD SnO channels is crucial for achieving high-performance p-type SnO TFTs.

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

Three Temperature Regimes in Subthreshold Characteristics of FD-SOI pMOSFETs From Room-Temperature to Cryogenic Temperatures

Three Temperature Regimes in Subthreshold Characteristics of FD-SOI pMOSFETs From Room-Temperature to Cryogenic Temperatures

Design of LDO circuit based on curvature compensation reference closed-loop stability

In this paper, a low dropout (LDO) circuit based on a curvature compensation benchmark and closed-loop stability is designed. This circuit compensates for the higher order term of VBE in a BJT through the subthreshold characteristic of MOSFET and achieves the effect of curvature compensation. The bandgap reference circuit provides a stable input voltage for the LDO circuit, while the source follower and adaptive bias circuit improve the response speed and closed-loop stability of the LDO circuit. The temperature drift coefficient of the bandgap circuit is 8.11 ppm/°C, the input voltage is 3–5 V, the output voltage is 2.8 V, and the linear adjustment rate is 0.22%.

Subthreshold Modeling of a Tunable CMOS Schmitt Trigger

In this article, the subthreshold characteristics of a tunable single input CMOS Schmitt trigger (ST) are modeled for the first time. The high-to-low and low-to-high hysteresis transition points are analytically determined as a function of the tuning voltages and the transistors’ geometrical parameters. The derived expressions allow to design the ST with desired hysteresis width in subthreshold region. Furthermore, the proposed model allows to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions also provide physical insight into the circuit behavior, by predicting the effect of supply voltage and temperature variations on the hysteresis width. The model is validated through simulations, and the maximum error between the analytical and simulated transition points is less than 5%. The model is also experimentally validated with an ASIC fabricated in AMS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu \text{m}$ </tex-math></inline-formula> CMOS process. The maximum error between the analytical and measured transition points is below 6%. The analytical model allows performance optimization in subthreshold region for low power applications.

Remarkable Reduction in IG with an Explicit Investigation of the Leakage Conduction Mechanisms in a Dual Surface-Modified Al2O3/SiO2 Stack Layer AlGaN/GaN MOS-HEMT.

We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal-oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric acid (HCl) with post-gate annealing (PGA) modulation at 400 °C for 10 min. A remarkable reduction in the reverse gate leakage current (IG) up to 1.5×10-12&amp;nbsp;A/mm (@ VG = -12 V) was observed in the stack layer MOS-HEMT due to the combined treatment. The performance of the dual surface-treated MOS-HEMT was significantly improved, particularly in terms of hysteresis, gate leakage, and subthreshold characteristics, with optimized gate annealing treatment. In addition, an organized gate leakage conduction mechanism in the AlGaN/GaN MOS-HEMT with the Al2O3/SiO2 stack gate dielectric layer was investigated before and after gate annealing treatment and compared with the conventional Schottky gate. The conduction mechanism in the reverse gate bias was Poole-Frankel emission for the Schottky-gate HEMT and the MOS-HEMT before annealing. The dominant conduction mechanism was ohmic/Poole-Frankel at low/medium forward bias. Meanwhile, gate leakage was governed by the hopping conduction mechanism in the MOS-HEMT without gate annealing modulation at a higher forward bias. After post-gate annealing (PGA) treatment, however, the leakage conduction mechanism was dominated by trap-assisted tunneling at the low to medium forward bias region and by Fowler-Nordheim tunneling at the higher forward bias region. Moreover, a decent product of maximum oscillation frequency and gate length (fmax × LG) was found to reach 27.16 GHz∙µm for the stack layer MOS-HEMT with PGA modulation. The dual surface-treated Al2O3/SiO2 stack layer MOS-HEMT with PGA modulation exhibited decent performance with an IDMAX of 720 mA/mm, a peak extrinsic transconductance (GMMAX) of 120 mS/mm, a threshold voltage (VTH) of -4.8 V, a higher ION/IOFF ratio of approximately 1.2×109, a subthreshold swing of 82 mV/dec, and a cutoff frequency(ft)/maximum frequency of (fmax) of 7.5/13.58 GHz.

Improved Subthreshold Characteristics by Back-Gate Coupling on Ferroelectric ETSOI FETs

In this work, extremely thin silicon-on-insulator field effective transistors (ETSOI FETs) are fabricated with an ultra-thin 3 nm ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer. Furthermore, the subthreshold characteristics of the devices with double gate modulation are investigated extensively. Contributing to the advantages of the back-gate voltage coupling effects, the minimum subthreshold swing (SS) value of a 40 nm ETSOI device could be adjusted from the initial 80.8–50 mV/dec, which shows ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is demonstrated. This work shows the feasibility of FE ETSOI FET for ultra-low-power applications with dynamic threshold adjustment.

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

Subthreshold Schottky-contacted carbon nanotube network film field-effect transistors for ultralow-power electronic applications

Ultralow-power electronics is critical to wearable, portable, and implantable applications where the systems could only have access to very limited electrical power supply or even be self-powered. Here, we report on a type of Schottky barrier (SB) contacted single-walled carbon nanotube (SWCNT) network film field-effect-transistors (FETs) that are operated in the subthreshold region to achieve ultralow-power applications. The thin high-k gate dielectric and the overlap between the gate and the source electrodes offer highly efficient gate electrostatic control over the SWCNT channel and the SB at the source contact, resulting in steep subthreshold switching characteristics with a small subthreshold swing (∼67 mV dec−1), a large current on/off ratio (∼106), and a low off-state current (∼0.5 pA). A p-channel metal-oxide-semiconductor inverter built with the subthreshold SB-SWCNT-FETs exhibits a well-defined logic functionality and small-signal amplification capability under a low supply voltage (∼0.5 V) and an ultralow power (∼0.05 pW μm−1). The low-voltage and deep subthreshold operations reported here could lay an essential foundation for high-performance and ultralow-power SWCNTs-based electronics.

Improved Electrical Characteristics of AlGaN/GaN High-Electron-Mobility Transistor with Al2O3/ZrO2 Stacked Gate Dielectrics.

A metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed based on using a Al2O3/ZrO2 stacked layer on conventional AlGaN/GaN HEMT to suppress the gate leakage current, decrease flicker noise, increase high-frequency performance, improve power performance, and enhance the stability after thermal stress or time stress. The MOS-HEMT has a maximum drain current density of 847 mA/mm and peak transconductance of 181 mS/mm. The corresponding subthreshold swing and on/off ratio are 95 mV/dec and 3.3 × 107. The gate leakage current can be reduced by three orders of magnitude due to the Al2O3/ZrO2 stacked layer, which also contributes to the lower flicker noise. The temperature-dependent degradation of drain current density is 26%, which is smaller than the 47% of reference HEMT. The variation of subthreshold characteristics caused by thermal or time stress is smaller than that of the reference case, showing the proposed Al2O3/ZrO2 stacked gate dielectrics are reliable for device applications.

Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2.

Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS2 FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.

Cell-type-specific integration of feedforward and feedback synaptic inputs in the posterior parietal cortex

The integration of feedforward (sensory) and feedback (top-down) neuronal signals is a principal function of the neocortex. Yet, we have limited insight into how these information streams are combined by individual neurons. Using a two-color optogenetic strategy, we found that layer 5 pyramidal neurons in the posterior parietal cortex receive monosynaptic dual innervation, combining sensory inputs with top-down signals. Subclasses of layer 5 pyramidal neurons integrated these synapses with distinct temporal dynamics. Specifically, regular spiking cells exhibited supralinear enhancement of delayed-but not coincident-inputs, while intrinsic burst-firing neurons selectively boosted coincident synaptic events. These subthreshold integration characteristics translated to a nonlinear summation of action potential firing. Complementing electrophysiology with computational modeling, we found that distinct integration profiles arose from a cell-type-specific interaction of ionic mechanisms and feedforward inhibition. These data provide insight into the cellular properties that guide the nonlinear interaction of distinct long-range afferents in the neocortex.

Improved DC Performance of Nanotube Junctionless Field-Effect Transistors with Dielectric Pocket Integration

In this paper, a nanotube architecture of Junctionless FET (JLFET) is investigated wherein it is observed that the performance characteristics of JLFET are improved by introducing Dielectric Pockets into the device near the source-channel and channel-drain interfaces by coming up with a novel structure of nanotube junctionless FET (NTJLFET) called as Dielectric Pocket-NTJLFET (DP-NTJLFET). Using TCAD tool, the proposed DP-NTJLFET has been simulated for a channel length of 20 nm in order to consider and show the improvement in various short-channel effects. The inclusion of Dielectric Pockets into the device significantly reduced the OFF-state current, which eventually improved the current switching ratio (∼2600%) for a pocket length and thickness of 4 and 7 nm, respectively. Further, the proposed device exhibits an improved subthreshold swing characteristics and a better measure of DIBL (improved by ∼12%) for DP-NTJLFET as compared to the conventional NTJLFET. As a result of achieving low OFF-state current, the proposed DP-NTJLFET may be found suitable for the future low-power applications.

Design and investigation of dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal pocket TFET device as a label-free biosensor

In this article, a dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal source pocket tunnel field-effect transistor (DM-TMGOS-ZHP-TFET) structure has been investigated for the application of label free-biosensor. This work explores the advantage of gate work function engineering along with the gate-oxide-stack approach for the ZHP-TFET for the first time. An asymmetric nano-cavity is created adjacent to the source-channel junction to immobilize the target biomolecules conjugation to the proposed device. The sensitivity of the device is thoroughly investigated in terms of average subthreshold swing (SS), threshold voltage (V th) and the switching ratio (I on/I off) of the proposed device with the variation of the dielectric constant value inside the nano-gap under the gate electrode. The device characteristics are investigated with different combinations of metal work functions to match the desired feature and sensitivity of the device. In addition, the sensitivity analysis of the proposed device is analyzed in the presence of both positive and negative charged biomolecules in the cavity region to study the charge effect on label-free detection of the device. A comparative study is conducted between a single metal gate (SMG) ZHP-DM-TFET biosensor with the DM-TMGOS-ZHP-TFET biosensor explores the advantage of gate-work function engineering with a gate-oxide-stack approach. Interestingly the DM-TMGOS-ZHP-TFET biosensor shows superior results with a high current ratio sensitivity of 103 which is ten times more than the SMG-ZHP-DM-TFET biosensor and this device also exhibits low subthreshold characteristics.

WO3 Passivation of Access Regions in Diamond MOSFETs

We study the impact of access region passivation on the electrical characteristics of hydrogen-terminated diamond MOSFETs with tungsten Carbide (WC) edge contacts. Our experiments reveal a significant improvement to both contact and extrinsic channel sheet resistance once the access regions are passivated with WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , indicating that WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is an effective surface transfer-doping agent. We analyze a peculiar bump that appears in the subthreshold characteristics of the devices that prevents their effective turn-off. The bump is found to be mitigated when the access regions are passivated by WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . Poisson–Schrödinger (P–S) simulations suggest that this bump arises from the field-effect action by the gate over the access region immediately adjoining the gate. This parasitic field effect arises when the surface is unpinned and with a light hole concentration. Owing to its increased surface transfer doping, the use of WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> as surface passivation is effective in delivering a sharp device turn-off.

Ternary Logics Based on 2D Ferroelectric-Incorporated 2D Semiconductor Field Effect Transistors

Ternary logic has been proven to carry an information ratio 1.58 times that of binary logic and is capable to reduce circuit interconnections and complexity of operations. However, the excessive transistor count of ternary logic gates has impeded their industry applications for decades. With the modulation of the ferroelectric negative capacitance (NC) properties on the channel potential, MOSFETs show many novel features including steep subthreshold swing and non-saturation output characteristics, based on which an ultra-compact ternary inverter can be achieved. Compared with traditional bulk materials, layered 2D materials and 2D ferroelectrics provide a clean interface and better electrostatic control and reliability. Even though ultra-low SS (∼10 mV/dec) has been experimentally demonstrated in ferroelectric-negative capacitance-incorporated 2D semiconductor (NC2D) FETs, the available models are still rare for large-scale circuit simulations. In this study, the superb electrical properties of pure 2D material stack-based NC2D FETs (layered CuInP2S6 adopted as the 2D ferroelectric layer) are investigated through device modeling based on the Landau–Khalatnikov (LK) equations in HSPICE. We managed to realize an ultra-compact ternary inverter with one NC2D-PMOS (WSe2) and one NC2D-NMOS (MoS2) in HSPICE simulations, whose transistor count is significantly reduced compared with other counterparts. We also proposed a novel input waveform scheme to solve the hysteresis problem caused by ferroelectric modulation to avoid logic confusion. Additionally, the power consumption and propagation delay of the NC2D-based ternary inverter are also investigated. This work may provide some insights into the design and applications of ferroelectric-incorporated 2D semiconductor devices.