Substrate Pad Research Articles

Electro-migration Behavior in Eutectic Sn-Bi Flip Chip Solder Joints with Cu-Pillar Electrodes

This paper discusses electro-migration behavior of eutectic Sn-Bi solder with Cu-pillar bumps. Two types of under bump metal (UBM) of organic substrate were studied, that is, Cu pad and electroless Ni/Au plated on Cu pad. The current density was 4x104A/cm2 at 125 and 150 degree C. Bi quickly migrated to accumulate on the anode side(Cu-pillar) and Sn migrated to the cathode side (Substrate pad). Both the case of surface finishes, although the resistivity was increased to approximately 80 % during approximately 80 hours, it was stabilized more than 2800 hours and there were no electrically break failure. From the cross-sectional analyses of eutectic Sn- Bi solder joints after the test, it was found that Bi layer and intermetallic compound (IMC) behaved as the barriers of the Cu atom migration into Sn solder.

Experimental birth of a maar–diatreme volcano

Maar–diatreme eruptions are hazardous to people and infrastructure, and are also linked to the formation of the kimberlitic variety of diatremes, which is important economically. Processes occurring in the subsurface diatreme and their relation to surface eruptions are not yet well understood. We conducted field-scale experiments using analog materials to shed more light on these processes, especially the formation of the proto-diatreme during the first explosions of a maar eruption. Specifically, a series of buried explosions in a prepared, layered substrate (pad) produced craters, extra-crater deposits and sub-crater deposits analogous to volcanic maar craters, tephra rings and incipient diatremes. Post-explosion substrate excavation revealed that single large explosions produce sub-crater deposits extending nearly to the crater-rim crest. The same energy divided into three blasts, either co-located or at different depths with the same epicenter, produced narrower and sometimes deeper sub-crater deposits even though the final sizes of the craters were similar to that produced by the single large blast. The sub-crater deposits have an upper zone with domains from different substrate depths, and an underlying zone distinguished primarily by being more loosely packed than the original substrate. Videos show surface motion extending beyond the post-shot crater rim, and largely vertical ejection and fallback of material into the footprint of these deposits, especially for the explosions that occurred below optimal depth of burial. We infer that much of the loosely packed material was disassembled, vertically transported to different heights during the explosions, then fell back without significant relative lateral movement of grains. However, subvertical fallback did produce apparent cross-cutting structures in shallow sub-crater deposits. One explosion ejected material from the deepest substrate horizon, but it was redeposited only within the crater and is unrepresented in the ejecta rim. Implications of the experiments for maar–diatreme volcanoes, including some kimberlite pipes, are as follows: (1) vertical focusing of deep explosions in the diatreme explains the deficit of deep wallrock lithics observed at maar volcanoes; (2) direct vertical fallback is possibly an important process forming diatreme deposits, especially during the earliest stages; and (3) even in our limited simulation the number and scaled depth of explosions clearly affect proto-diatreme size and structure.

Effects of moisture absorption on anisotropic conductive films interconnection for flip chip on flex applications

This paper reports the investigations into the moisture induced failures in Flip-Chip-on-Flex interconnections using Anisotropic Conductive Films (ACFs). Both experimental and modelling methods were applied. In the experiments, the joint resistance was used as a quality indicator and was measured continuously during the autoclave test. The test condition was set as 121^oC, 100%RH and 2atm. The results showed that the joint resistance of the ACF flip chip increased during the tests and nearly 25% of the joints were found open after 168h' testing. Visible conduction gaps between the adhesive and substrate pads were observed. Cracks at the adhesive/flex interface were also found. In order to have a better understanding of the experimental results, 3D Finite Element (FE) models of the ACF assembly were constructed and a macro-micro modelling technique was used to overcome the difficulty caused by the multi-length scale in the ACF assembly. The moisture diffusion and moisture-induced stresses in the ACF flip chip during the autoclave test were predicted. Modelling results are consistent with the findings in the experimental work.

The effect of micro via‐in pad design on surface‐mount assembly defects: part II – voiding and spattering

PurposeThe purpose of this paper is to propose a solution procedure to minimize/eliminate voiding and spattering defects in the assembly of 0201 chip components with micro via‐in pads and 95 wt.%Sn‐5 wt.%Sb solder alloy.Design/methodology/approachIn total, four different micro via‐in pad designs were compared (via‐hole opening size): ultra small via‐in pads (d: 10 μm), small via‐in pads (d: 20 μm), and large via‐in pads (d: 60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder systems. Potential factors, such as the preheat conditions of the reflow profile and stencil aperture size, which might affect voiding and spattering in solder joints with micro via‐in pad, were investigated. Solder voiding frequency and size were also determined from X‐ray inspection and sample cross‐section analysis.FindingsThe results indicated that larger via‐holes were seen to create bigger voiding than smaller via‐holes. For smaller via‐holes, spattering is a greater problem than voiding in solder joints. Ultra small via‐in pads generated higher spattering compared to no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing voiding and flux spattering, and provided a wide process window for the selection of process parameters. It is also indicated that spattering was found to rapidly reduced with both increasing stencil opening size and use of reflow profile with long‐preheat conditions.Originality/valueThe findings provide certain process guidelines for surface‐mount assembly with via‐in pad substrate design. The strategy is to prevent voiding and spattering by adopting capped via‐in pads, if possible, when applying micro via with the 95 wt.%Sn‐5 wt.%Sb solder alloy system.

Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni3P and (Cu,Ni)6Sn5 after thermal aging, while the substrate pad region contains Cu3Sn and (Cu,Ni)6Sn5. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)6Sn5 on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm2/h, 0.1423 μm2/h, and 0.4463 μm2/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.

Electromigration Reliability of Glass Ceramic Multilayer Substrate with Various Surface Finishes

The process speed of high-end servers and supercomputers are steadily increasing. As a result, the backbone of the high speed processing, such as high-end LSI (flip-chip type), and associated substrate circuits is also becoming more dense and miniaturized, while supporting higher current densities. However, recent studies indicate that the higher current density triggers an electromigration (EM) at the solder bumps connecting the under bump metallurgy (UBM) of the flip-chip pad (e.g. Ni) and substrate pads (e.g. Ni/Au). This electromigration leads to voids within the solder joints, which may result in an open circuit. As of result, the life-cycle of the packaged devices is shortened. Thus solution to the EM issue is critical. To respond to such concerns, we have studied the mechanism of the void development, by closely examining differences in diffusion rate among the connective metals - within the pads and the solders. We have mitigated the EM occurrence by reducing the differences in diffusion rate by utilizing high purity Cu for the substrate metallization pads, Cu exhibits a diffusion rate similar to Sn used in solder bumps. Also, solder wettability was improved by utilizing a solder on pad (SOP) construction. As of result we were able to successfully demonstrate an improved life-cycle of the flip-chip solder joints, while accommodating a higher current density. Furthermore, a glass ceramic substrate was used for our study. Since this particular glass ceramic substrate has a coefficient of thermal expansion of 11.8ppm/K, there is an improvement in 1st and 2nd level reliabilities associated with thermal stress from device heat generation. At the same time, it possesses a dielectric constant of 5.8, which is conductive with superior electrical performance (high speed and high frequency). Thus, this glass ceramic substrate is capable of supporting increases in current density, while sustaining high reliability.

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

Development of an AC Electric Field-Applied Tribochemical Polishing Technology to Promote High-Efficiency Polishing for Glass Substrates (Image Analysis of Dynamical Slurry Behaviours and Polishing Characteristics under AC Electric Field)

This paper deals with the investigation conducted on the mechanism of the polishing technology, to which AC electric field is applied. For the analysis of the slurry dynamical behaviors, we used a digital image processor. In this research, we have also worked to develop a novel high-efficiency polishing technology applying AC electric field for the glass substrates for IT devices. When AC electric field was applied to, the slurry behavior was found to have better stability than the one without AC electric field. Furthermore, good polishing rates were obtained under high-relative rotation speed between the glass substrates and polishing pad. This suggests that the friction heat generated between the glass substrate and polishing pad, which promote tribochemical reactions, improves polishing rate. This latest polishing technology makes the removal rate two times better than the conventional polishing and produces excellently smooth surface.

Direct evidence of phospholipids in gecko footprints and spatula–substrate contact interface detected using surface-sensitive spectroscopy

Observers ranging from Aristotle to young children have long marvelled at the ability of geckos to cling to walls and ceilings. Detailed studies have revealed that geckos are 'sticky' without the use of glue or suction devices. Instead, a gecko's stickiness derives from van der Waals interactions between proteinaceous hairs called setae and substrate. Here, we present surprising evidence that although geckos do not use glue, a residue is transferred on surfaces as they walk-geckos leave footprints. Using matrix-free nano-assisted laser desorption-ionization mass spectrometry, we identified the residue as phospholipids with phosphocholine head groups. Moreover, interface-sensitive sum-frequency generation spectroscopy revealed predominantly hydrophobic methyl and methylene groups and the complete absence of water at the contact interface between a gecko toe pad and the substrate. The presence of lipids has never been considered in current models of gecko adhesion. Our analysis of gecko footprints and the toe pad-substrate interface has significant consequences for models of gecko adhesion and by extension, the design of synthetic mimics.

Research on Rapid Detection of Vitamin C with an Optic Sensor

Based on the spectral absorption/reflection principles, a home-made optic sensor which included substrate, filtration membrane, reaction film and absorbent pad has been proposed and established to detect vitamin C rapidly. In the experiment, ferric ion was reduced to ferrous ion by vitamin C in samples, the reaction film color turned from yellow to orange-red upon the binding reaction of ferrous ion to phenanthroline. Results demonstrated that vitamin C concentrations were proportional to L values of the L a b color system. A good linearity was presented in the range of 0.25-2500 μg/mL. The correlation coefficient(r) was 0.980 and the testing time was about 2 min at room temperature.

Direct parameter-extraction method for MOSFET noise model from microwave noise figure measurement

A new method for the determination of the four noise parameters of the metal oxide semiconductor field effect transistors (MOSFETs) based on the noise figure measurement system without microwave tuner is presented. The noise parameters are determined based on a set of analytical expressions of noise parameters by fitting the measured noise figure of the active device. These expressions are derived from an accurate small signal and noise equivalent circuit model, which takes into account the substrate parasitics, pad capacitances, and series inductances. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for 0.5 × 5 × 16 μm, 0.35 × 5 × 16 μm and 0.18 × 5 × 16 μm (gate length × number of gate fingers × unit gate width) MOSFETs.

Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

PoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is required. The C4 (Controlled Collapse Chip Connection) flip chip technology is widely used in area array flip chip packages. The C4 was named after the four initial characters which are C of Controlled Collapse Chip Connection. The collapse of the molten solder is controlled by the individual opening of solder resist on each pad on the substrate so that the chip can be connected onto the substrate. However, C4 is not suitable in the ultra-fine-pitch flip chips because the such a individual opening which is suitable for the ultra-fine-pitch cannot be made on the substraete. Instead of the C4 flip chip technology, the new interconnection technique was developed using the solder capped Cu pillar bumps. It is very easy to control the space between the die and the substrate by adjusting the Cu pillar height even when a large slit window opening exists on a group of pads on the substrate. Since the collapse control of the solder bumps is not necessary, we call the process C2 (Chip Connection). The C2 was named after the two initial characters which are C of Chip Connection. The solder capped Cu pillar bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), by reflow with no-clean processes. This technology creates the SMT (Surface Mount Technology)/flip chip hybrid assembly for SoP (System on Package) use. We have produced 50 μm pitch interconnections and observed the micro structure and tested their reliability. Some voids in the solder joint were observed after the reflow process. The results of warpage measurements and FEM (Finite Element Method) analyses suggest that these voids are the shrinkage voids caused by the wide temperature range of the solder liquid phase and the substrate warpage. Since they are not the stress induced voids, they didn't affect the reliability test. The increase in interconnection resistance during the reliability test was compared between the C2 interconnection and Au stud-solder interconnection. Since the resistance increase of the C2 interconnection is much smaller than that for the Au stud-solder interconnection, it is clear that the C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the TC (Thermal Cycle) test. In addition to the fine-pitch interconnections, a die thickness of 70 μm is required to reduce the final stack height. The reliability performance of the C2 flip chip with the die thicknesses 20 μm, 70 μm and 150 μm was also discussed using a PEG (Post-Encapsulation Grinding) method in which the die is ground to less than 70 μm after joining and underfilling. Finally the electromigration tests were performed on the 80 μm pitch C2 interconnection. The tests showed that the solder capped Cu pillar structure has high endurance against electromigration and no failure data was recorded up to 1,000 hrs with several electromigration conditions regardless the direction of electron flow.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

Electro-migration Behavior in Micro-joints of Sn-57Bi solder and Cu Post Bumps

The bonding technique for high density Flip Chip(F.C.) packages requires a low temperature and a low stress process to achieve high reliability of the micro joining. Sn-Bi solder has been noted as a low temperature bonding material. Electromigration behavior of Sn-57wt%Bi flip chip interconnection with Cu post bumps was investigated. The flip chip bumps used for this experiments consisted of Cu post formed with plating and Sn-57wt%Bi solder. Two types of under bump metal(UBM) of organic substrate were studied, that is, electroless Ni(6μm)/Au(0.5μm) on Cu pad and Cu pad. Electron flow to induce the electro-migration was from organic substrate side (Cu pad) to chip side (Cu post) with current density of 40000A/cm2 at 125 degree C. At both types of the UBM, Bi migrated and accumulated to the anode side (Cu post) and Sn migrated to the cathode side (substrate pad). Each interconnect resistance has increased to about 25% and 46% within 100 hours, respectively. However, after more than 3000 hours, they were stabilized. With Ni/Au UBM pad, Cu3Sn/Cu6Sn5 intermetallic compounds (IMCs) were formed at the Cu bump side. And under the Bi layer Cu6Sn5/Ni-Sn compounds were formed. But we didn’t observe the failure like cracks or voids at the Ni layer. With Cu pad, only Cu3Sn IMC at the Cu bump side and under the Bi layer Cu6Sn5/Cu3Sn compounds were formed after 4000 hours. Although the voids were observed at Cu3Sn/Cu interface, good electrical connection was obtained.

Damage Mechanics Model for Solder/Intermetallics Interface Fracture Process in Solder Joints

The relatively brittle solder/IMC interface fracture process in reflowed solder joints is examined using finite element (FE) method. The interface decohesion is described using a traction-separation quadratic failure criterion along with a mixed-mode displacement formulation for the interface fracture event. Reflowed Sn-4Ag-0.5Cu (SAC405) solder ball on OSP copper pad and orthotropic FR4 substrate under ball shear push test condition at 3000 mm/sec is simulated. Unified inelastic strain constitutive model describes the strain rate-response of the SAC405 solder. Comparable simulated and measured load-displacement values during solder ball shear push test serve as validation of the damage-based FE model. Results indicate a nonlinear damage evolution at each material point of the solder/IMC interface during the ball shear push test. The normal-to-shear traction ratio at the onset of the interface fracture is 1.59 indicating significant induced bending effect due to shear tool clearance. Rapid interface crack propagation is predicted following crack initiation event with the average crack speed up to 24.6 times the applied shear tool speed. The high stress concentration along the edge of the solder/IMC interface facilitates local crack initiation and dictates the shape of the predicted dynamic crack front.

PBGA Cost Reduction by Reducing Plated Au Thickness of Substrate Pads

In the past decade, we have witnessed the significant increase of gold price. Coupled with continuous price decrease of electronic products, the reduction of gold consumption has been explored in every possible area. This paper is related to reducing gold consumption on wire bonding pads of low density interconnect substrates. A layer of gold is plated on the substrate pads with typical minimum thickness of 0.5um to facilitate wire bonding process using gold wire. The objective of this study was to reduce gold thickness on the substrate pad to 0.3um minimum without compromising wire bond integrity. DOE considering different substrate sources wire bonded by different assembly suppliers were conducted. Wire bonding process optimization was followed by package level reliability stress testing, heat aging, and board level solder joint reliability testing was carried out for validation. The results showed plated gold thickness on the wire bond substrate pads can be reduced to a minimum of 0.3um without compromising package reliability performance. With the success of thinner gold on the substrate pads, we can use the same natural resources - gold to build more units, 'better for environment, if we consume less'

Electromigration Performance of Pb-Free μPILR™ Flip-Chip Packages

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages. Electromigration performance of μPILR interconnects has shown a significant improvement and noticeably delayed electromigration induced failures. Voids initially begin to appear at Cu6Sn5 and solder interface on the die side, with eventual open failure due to excessive void formation along with a severe depletion of Cu Under Bump Metallization (UBM). No failure was observed on the substrate side of the interconnect regardless of the current direction. The enhanced performance of the μPILR interconnect along with other reliability benefits makes it an excellent alternative to conventional solder joints including thin film stack UBMs, thicker copper UBM as well as copper pillar on die.

ENIG Corrosion Induced by Second-Phase Precipitation

Materials analysis of a flip-chip package lot with solder bump interconnect failures revealed a new mechanism for corrosion of electroless nickel immersion gold surface finish. Detailed scanning and transmission electron microscopy (SEM and TEM) in conjunction with focused ion beam microscopy and electron dispersion analysis of the unsoldered ball grid array substrate pads on packages that exhibited flip-chip solder bump interconnect failures revealed an unusual and subtle defect in the original Ni(P) layer, which was ultimately responsible for flip-chip joint failure. Detailed TEM analysis of the defect regions showed that they consisted of Ni(P) particles of slightly different composition than the bulk Ni(P) layer. Microstructure changes around these incorporated particles indicated that the second-phase particles were deposited from the plating bath during the Ni(P) growth stage. The second-phase particles provided additional surface area for nucleation and growth of Ni(P). Ultimately, a low-density boundary region in the growing Ni(P) layer formed where the particle-induced growth front and the planar Ni(P) film growth front intersected. This low-density interface eventually terminated at the surface of the Ni(P) layer. In addition the growth from the second-phase particle created localized surface topology that was different than that of the surrounding Ni(P) layer. The low-density interfaces as well as the surface topology led to enhanced corrosion of the Ni(P) layer when exposed to the immersion gold plating process. In some cases the corrosion was severe enough to create voids in the Ni(P) layer. The exposed, oxidized Ni(P) surfaces in and around these enhanced corrosion regions did not wet when exposed to solder. This led to degradation in the strength of the solder joint and subsequent solder interconnect failure.

Effect of multiple reflow cycles on ball impact responses of Sn‐Ag‐Cu solder joints

PurposeThe purpose of this paper is to report the effect of multiple reflow cycles on ball impact test (BIT) responses and fractographies obtained at an impact velocity of 500 mm/s on Sn‐4Ag‐0.5Cu solder joints.Design/methodology/approachSolder balls were mounted on copper substrate pads with immersion tin surface finish, supplied by two vendors. For these particular test vehicles and test conditions, fracture near the interface between the interfacial Cu6Sn5 intermetallic compound (IMC) and copper pad was identified as the only failure mode induced by BIT.FindingsMeasurement results indicate that BIT characteristics in general degrade as the number of reflow cycles increases. Furthermore, scanning electron microscopy observations show that the thickness and grain size of interfacial Cu6Sn5 increase with increasing number of reflow cycles. This correlation confirms the familiar notion that a thicker Cu6Sn5 degrades the interfacial strength.Originality/valueThere are few reports that can attribute failure directly to the IMC(s) at the interface. This paper, however, successfully correlates the weakening solder joints with the thickening and shape changes of IMC(s) in a direct way.

Electromigration Reliability of 96.5Sn–3Ag–0.5Cu Flip-Chip Solder Joints With Au/Ni/Cu or Cu Substrate Pad Metallization

Designed experiments were conducted in this paper to study the effect of Au/Ni/Cu or Cu substrate pad metallization on the electromigration reliability of 96.5Sn–3Ag–0.5Cu flip-chip solder joints with Ti/Ni(V)/Cu under bump metallurgy (UBM) under a current stressing condition with an average current density of around 5 kA/cm2 at an ambient temperature of 150°C. Cross-sectional observations on current-stressed solder joints indicate that although Cu metallization results in severe voiding compared with Au/Ni/Cu metallization on the substrate side of the solder joint, the dominant failure has been identified as UBM consumption, and test vehicles with Cu metallization exhibit better electromigration reliability than those with Au/Ni/Cu metallization. The stronger durability against current stressing for test vehicles with Cu metallization may attribute to the lower UBM consumption rate due to the continuous Cu diffusion toward UBM as a result of the concentration gradient. The consumption of UBM is faster for test vehicles with Au/Ni/Cu metallization because Cu diffusion from the substrate pad is retarded by the Ni barrier.