This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface, as a function of the gate length and substrate bias, on both the front threshold voltage (Vthf) and subthreshold slope (S), for sub-32nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145nm (UTB) or thin 11.5nm (UTB2). This study details for the first time, the important impact of the substrate/BOX interface regime variations with gate length from 1μm down to 25nm, substrate bias and BOX thickness together, on the mean channel position into film and its related impact on the electrical parameters Vthf and S. Experimental results and conclusions are also completed and enlightened by ATLAS simulations and analytical modeling.
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