Substrate Coupling Effects Research Articles

Simulation of substrate coupling for mobile communications SoC – A 20 GHz VCO case study

An innovative substrate coupling simulation methodology with on-the-fly extraction and validation of CMOS substrate parasitic elements, combining boundary element method (BEM) with a computational python based physical layout extraction and RC modeling method, is presented in this work. The proposed methodology is seamlessly integrated into the standard virtuoso based custom circuit design flow and allows the designer to extract fast and accurate a substrate RC mesh, valid from DC to GHz, enabling crosstalk impact estimation and gaining insight on substrate coupling effects from the early stage of the design process until the prototype phase. The proposed substrate crosstalk modeling flow is validated using a 20 GHz VCO circuit as a crosstalk victim. The VCO vehicle is designed using a 65 nm RFCMOS process and the respective RF devices of the specific PDK are used. The PCB transmission line and the package parasitics must be considered as to achieve more accurate and realistic simulation results. The simulation scheme is set using a layout footprint test case and two separate signal injection tap points, each at a certain distance from the VCO victim. This simulation scheme can provide various substrate signal crosstalk scenarios by injecting signals that consist of multiple frequencies into the substrate. Three simulation analysis types, Transient, QPSS and ENVLP, are performed as to be able to designate which analysis is the most suitable for crosstalk simulation in terms of simulation time, accuracy and compatibility. Finally, as a sanity check and methodology validation, crosstalk isolation trends with respect to the aggressor distance and the substrate signal frequency are extracted and compared with the State-of-the-Art results available in literature.

System on Chip Noise Integrity Simulation

In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

Modeling method for grounded coplanar waveguide with vector fitting technique

AbstractIn this article, a semiempirical equivalent circuit model of the grounded coplanar waveguide (GCPW) based on the vector fitting is proposed for the first time, which improves the accuracy in high frequency. It offers an effective solution for the millimeter GCPW modeling. This model takes into account nonideal effects such as skin effect and substrate coupling effect, which realizes the combination of numerical method and physical meaning. The method we propose aims to use sequential quadratic programming algorithm to solve strictly passive problems. Good agreement is obtained between the modeled and measured data up to 40 GHz.

Pinning and Anharmonic Phonon Effect of Quasi-Free-Standing Bilayer Epitaxial Graphene on SiC.

Epitaxial graphene on SiC without substrate interaction is viewed as one of the most promising two-dimensional (2D) materials in the microelectronics field. In this study, quasi-free-standing bilayer epitaxial graphene (QFSBEG) on SiC was fabricated by H2 intercalation under different time periods, and the temperature-dependent Raman spectra were recorded to evaluate the intrinsic structural difference generated by H2 time duration. The G peak thermal lineshift rates dω/dT showed that the H2 intercalation significantly weakened the pinning effect in epitaxial graphene. Furthermore, the G peak dω/dT value showed a perspicuous pinning effect disparity of QFSBEG samples. Additionally, the anharmonic phonon effect was investigated from the Raman lineshift of peaks. The physical mechanism responsible for dominating the G-mode temperature-dependent behavior among samples with different substrate coupling effects was elucidated. The phonon decay process of different samples was compared as the temperature increased. The evolution from in situ grown graphene to QFSBEG was determined. This study will expand the understanding of QFSBEG and pave a new way for its fabrication.

Electrical modeling of tapered TSV including MOS-Field effect and substrate parasitics: Analysis and application

In this paper, a simple closed-form model identifying the electrical behavior of a taper through silicon via (TSV) is reported. The model is based on the Transmission Line Method (TLM) and 3D electromagnetic simulations. The usefulness of the modeling approach is validated through measurements on some test structures over a wide range of frequencies from DC to 10 ​GHz. The substrate coupling and MOS effects are included in the electrical description of the 3D system as they are no longer negligible at high-frequency range operation. The efficient 3D-TLE (Transmission Line Extractor) by INL (Institute of Nanotechnology of Lyon) tool is used to extract the impedance of contacts and TSVs. Moreover, as an application of this extractor, a 26GHz/2 ​GHz bandwidth TSV based RF filter is proposed and designed.

Experimental demonstration of ultra-large-scale terahertz all-dielectric metamaterials

All-dielectric metamaterials have emerged as a promising platform for low-loss and highly efficient terahertz devices. However, existing fabrication methods have difficulty in achieving a good balance between precision and cost. Here, inspired by the nano-template-assisted self-assembly method, we develop a micro-template-assisted self-assembly (MTAS) method to prepare large-scale, high-precision, and flexible ceramic microsphere all-dielectric metamaterials with an area exceeding 900 cm×900 cm. Free from organic solvents, vacuum, and complex equipment, the MTAS method ensures low-cost and environmentally friendly fabrication. The ceramic microsphere resonators can be readily assembled into nearly arbitrary arrangements and complex aggregates, such as dimers, trimers, quadrumers, and chains. Finally, using the heat-shrinkable substrate and dipole coupling effect, a broadband reflector with a bandwidth of 0.15 THz and a reflection of up to 95% is demonstrated. This work provides a versatile and powerful platform for terahertz all-dielectric metamaterials, with potential to be applied in a wide variety of high-efficiency terahertz devices.

Effect of Substrate Coupling on the Performance and Variability of Monolayer MoS2 Transistors

We study the effect of substrate coupling on the variability and the device characteristics of monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> field-effect transistors (FETs). Our electrical measurement results reveal significant improvements of key FET device metrics and marked reduction of device variability with reducing the interfacial energy. We attribute the observed improvements of the device characteristics to the reduction of the interface trap density and the suppression of the charged impurity scattering. This study establishes the critical role of substrate coupling on the performance and variability of monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs.

A physics-aware methodology for equivalent circuit model extraction of TSV-inductors

TSV-inductor has become a viable on-chip inductor option to ensure low-power, low-cost, and high-integration. Thus, it is imperative to accurately and efficiently model the electrical behavior of a TSV-inductor. Unlike the conventional 3D electro-magnetic wave model that suffers from its incapability of efficient time-domain SPICE simulation, in this paper, a systematic equivalent circuit model extraction methodology is presented to accurate the model of on-chip TSV-inductors in 3D IC. The circuit topology is based on a π -circuit with additional branches accounting for substrate coupling, signal crosstalk, skin and proximity effects. The parasitics are then extracted from the measured network parameters using an improved vector fitting method. Experimental results show that the proposed methodology is able to achieve a TSV-inductor equivalent circuit with very high accuracy with up to 10−4 deviation in S parameter comparison and 0.024% relative error in quality comparison.

High-Performance MMIC Inductors for GaN-on-Low-Resistivity Silicon for Microwave Applications

Novel MMIC spiral inductors on GaN-on-low-resistivity silicon (LR-Si) substrates (σ <; 40 Ω · cm) are demonstrated with enhanced self-resonance frequency ( fSRF) and Q-factor. The developed technology improves inductor performance by suppressing substrate coupling effects using air-bridge technology above benzocyclobutene dielectric as an interface layer on the lossy substrate. A 0.83-nH spiral inductor with peak Q-factor enhancement of 57% (Q = 22 at 24 GHz) and maximum fSRF of 59 GHz was achieved because of the extra 5-μm elevation in air. An accurate broad-band model for the fabricated inductors has been developed and verified for further performance analysis up to 40 GHz. The proposed inductors utilize cost-effective, reliable, and MMIC-compatible technology for the realization of high-performance RF GaN-on-LR Si MMIC circuits for millimeter-wave applications.

CMOS substrate coupling modeling and analysis flow for submicron SoC design

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.

An efficient and simple compact modeling approach for 3-D interconnects with IC׳s stack global electrical context consideration

3D integration is considered to be the most promising solution to overcome challenges encountered currently in planar technologies. As an emerging technology, electrical compact models are notably required for 3D interconnects, including Through-Silicon Via (TSV), to accurately evaluate 3D system performances. However, 3D integration implies that the whole electrical context must be considered such as current paths or couplings between chip elements. Simple closed-form expressions describing the electrical models of some 3D ICs propagation lines are reported in this paper. The efficient modeling methodology described in this work is applied to various 3D test structures. The modeling approach׳s effectiveness is validated in a wide frequency range, from DC to 10GHz. Nevertheless, in the high frequency-domain, the substrate coupling effects are no longer negligible and must be also included in the overall 3D system electrical description. As a consequence, a substrate extraction method, relying on the Transmission Line Method (TLM) and the Green functions, is also proposed to model substrate networks. This extraction method is validated in the case of a coplanar waveguide atop a high-resistive substrate. Finally, the method is applied for timing analyses by means of Eye Diagrams performed on different TSV matrix configurations.

The underestimated thermal conductivity of graphene in thermal-bridge measurement: A computational study

The effect of substrate coupling on thermal conductivity of graphene is studied by using molecular dynamic simulations. It was found that heat flux along real suspended single-layer graphene is only 40% with respect to that in the ideal suspended single-layer graphene, due to remarkable temperature jump and thermal contact resistance at the contact region. With the strength of inter-layer (or graphene-substrate) interaction increases, the temperature jump increases and leads to further reduction in heat flux and the estimated thermal conductivity. Our results give a reasonable explanation to the underestimated thermal conductivity of graphene in thermal-bridge measurement.

Analysis of parasitic effects in triple‐well CMOS SPDT switch

A comparison between a conventional body floating single pole double throw (SPDT) CMOS switch design and a proposed switched gate floating CMOS SPDT switch design based on an analysis of parasitic effects is presented. In standard CMOS technology, the switched gate floating switch is analytically proved to have higher isolation owing to the alleviation of parasitic diode and substrate coupling effects in the operation state. The proposed switch maintains a similar insertion loss as conventional swithches while achieving an average of 6 dB isolation improvement over the operating frequency, which agrees well with the presented analysis.

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.

A Novel Transmission-Line Deembedding Technique for RF Device Characterization

A novel transmission-line deembedding technique is presented in this paper. With this technique, the left- and right-side ground-signal-ground probe pads can be extracted directly using two transmission-line test structures of length L and 2L. An additional through structure is designed using via-stack deembedding, which is unique among current deembedding methods. The advantages of the proposed method include the following: 1) smaller silicon area; 2) discontinuity between the pad and interconnect; 3) substrate coupling and contact effects; and 4) employment of via-stack deembedding. The proposed novel methodology is a great breakthrough in the area of ultrahigh-frequency deembedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave CPW transmission-line structures are placed on the interlevel metallization layers, as they are the most appropriate RF device for cascade-based deembedding method involving the via-stack deembedding technique. Experimental results have demonstrated that attenuation loss and wavelength can be optimized by changing the metal density and the position of the metal layer on the floating shields. Both measurement and electromagnetic-wave simulations were performed up to 50 GHz. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields.

Studies of Mg film and substrate coupling effects on hydrogenation properties

Changes of microstructure, phase composition and surface morphology were investigated for 1.5–2 μm thick nanocrystalline Mg films, which were sputter-deposited on quartz and stainless steel substrates and hydrogenated at 600 kPa in the temperature range 200–260 °C. The volume fraction of MgH 2 in Mg and changes of the surface topography were analyzed using X-ray diffraction and scanning electron microscopy analysis, respectively. Coupling processes occurring between the Mg film and the substrate were registered and correlated with hydrogenation properties. Due to strong coupling to stainless steel substrate, a fast and complete transformation of Mg into MgH 2 accompanied by film cracking and spontaneous crushing into nanometer-size powder was observed. For Mg films weakly coupled to the quartz substrate, a slow and partial transformation of Mg into MgH 2 and simultaneous film buckling followed by film detachment and flaking was registered.

System integration design in MEMS — A case study of micromachined load cell

One of the critical issues in large scale commercial exploitation of MEMS technology is its system integration. In MEMS, a system design approach requires integration of varied and disparate subsystems with one of a kind interface. The physical scales as well as the magnitude of signals of various subsystems vary widely. Known and proven integration techniques often lead to considerable loss in advantages the tiny MEMS sensors have to offer. Therefore, it becomes imperative to think of the entire system at the outset, at least in terms of the concept design. Such design entails various aspects of the system ranging from selection of material, transduction mechanism, structural configuration, interface electronics, and packaging. One way of handling this problem is the system-in-package approach that uses optimized technology for each function using the concurrent hybrid engineering approach. The main strength of this design approach is the fast time to prototype development. In the present work, we pursue this approach for a MEMS load cell to complete the process of system integration for high capacity load sensing. The system includes; a micromachined sensing gauge, interface electronics and a packaging module representing a system-in-package ready for end characterization. The various subsystems are presented in a modular stacked form using hybrid technologies. The micromachined sensing subsystem works on principles of piezo-resistive sensing and is fabricated using CMOS compatible processes. The structural configuration of the sensing layer is designed to reduce the offset, temperature drift, and residual stress effects of the piezo-resistive sensor. ANSYS simulations are carried out to study the effect of substrate coupling on sensor structure and its sensitivity. The load cell system has built-in electronics for signal conditioning, processing, and communication, taking into consideration the issues associated with resolution of minimum detectable signal. The packaged system represents a compact and low cost solution for high capacity load sensing in the category of compressive type load sensor.

Substrate coupling effect to transport in nanographene ribbon

Due to the components of electronics being developed on substrates, the substrate couplingto the conduction channel of electronics should be reasonably considered. We propose ananographene ribbon coupling with substrates to study the variation in conductivity andmagnetoresistance.

Interdevice isolation characteristics for design and fabrication of 60‐GHz WPAN SoCs

AbstractThe high interdevice isolation levels is one of the key technologies in the design and fabrication of 60‐GHz WPAN SoC. To obtain proper interdevice isolation levels, we have analyzed and measured substrate coupling effects with various isolation techniques like a trench and implant structure. From the analyzed and measured results, the feasibility of the implant has confirmed to be applicable to the mm‐wave SoC, and also derived an equivalent circuit form these results, which can be helpful to the design and fabrication of the 60‐GHz WPAN SoC. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1699–1702, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23470