Abstract

An innovative substrate coupling simulation methodology with on-the-fly extraction and validation of CMOS substrate parasitic elements, combining boundary element method (BEM) with a computational python based physical layout extraction and RC modeling method, is presented in this work. The proposed methodology is seamlessly integrated into the standard virtuoso based custom circuit design flow and allows the designer to extract fast and accurate a substrate RC mesh, valid from DC to GHz, enabling crosstalk impact estimation and gaining insight on substrate coupling effects from the early stage of the design process until the prototype phase. The proposed substrate crosstalk modeling flow is validated using a 20 GHz VCO circuit as a crosstalk victim. The VCO vehicle is designed using a 65 nm RFCMOS process and the respective RF devices of the specific PDK are used. The PCB transmission line and the package parasitics must be considered as to achieve more accurate and realistic simulation results. The simulation scheme is set using a layout footprint test case and two separate signal injection tap points, each at a certain distance from the VCO victim. This simulation scheme can provide various substrate signal crosstalk scenarios by injecting signals that consist of multiple frequencies into the substrate. Three simulation analysis types, Transient, QPSS and ENVLP, are performed as to be able to designate which analysis is the most suitable for crosstalk simulation in terms of simulation time, accuracy and compatibility. Finally, as a sanity check and methodology validation, crosstalk isolation trends with respect to the aggressor distance and the substrate signal frequency are extracted and compared with the State-of-the-Art results available in literature.

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