Submicron Complementary Metal Oxide Semiconductor Research Articles

Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model

Complementary Metal Oxide Semiconductor (CMOS) has always remained the dominant integrated circuit technology specifically for designing digital circuits. This paper examines the modelling (utilizing $\alpha$-power based MOSFET model), simulation (utilizing HSPICE simulation) and optimization (utilizing Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) techniques) of ultradeep submicron CMOS based digital inverter, performs insightful analysis and extracts formulas for the optimal transistor sizing. Additionally, the study serves as an implementation forum for the thermal analysis of transient characteristics of CMOS inverters at the ultradeep submicron technology node (at 300K and 400K). The results lie within the acceptable range of 1-10\%.

Quantum physics applied to modern optical metal oxide semiconductor transistor

In recent years, traditional complementary metal–oxide–semiconductor (CMOS) scaling techniques have begun to reach the technological limits of available materials. A revolution in block-to-block communication is necessary to meet the ever-growing demand for microprocessor computational power. On-chip optical communication has been designated as a promising solution to circumvent the CMOS scaling bottlenecks: second-order phenomenon, which causes significant interconnect delays, and the nonscalability of the thermal voltage, which becomes significant in submicron CMOS technology. The metal oxide semiconductor quantum well transistor, a silicon-on-insulator metal–oxide–semiconductor field-effect transistor device, with a channel thickness reduced to the single nanometer scale is examined. The nanometric gate oxide, silicon, and buried oxide heterostructure in the channel forms a quantum potential well, creating discrete sub-bands within the silicon layer. Inter-sub-band-transitions within the quantum well may allow for radiative recombination in indirect band gap materials.

A full 3D model of the modulation efficiency of a submicron complementary metal–oxide–semiconductor (CMOS)-compatible interleaved-junction optical phase shifter

The optimization of the performance of optical modulators requires reasonably accurate predictive models for key figures of merit. The interleaved PN junction topology offers the maximum mode/junction overlap and enables the most efficient modulators for depletion-mode operation. Due to the structure of such devices, accurate modeling must be fully three dimensional (3D), representing a nontrivial computational problem. A rigorous 3D model for the modulation efficiency of a silicon-on-insulator interleaved-junction optical phase modulator with submicron dimensions is presented herein. The drift–diffusion and Poisson’s equations are solved on a 3D finite-element mesh, while Maxwell’s equations are solved using the finite-difference time-domain method on 3D Yee cells. The entire modeling process is presented in detail, and all the coefficients required by the model are presented. The model validation suggests < 10% root-mean-square (RMS) error.

Neural Monitoring With CMOS Image Sensors.

Implantable image sensors have several biomedical applications due to their miniature size, light weight, and low power consumption achieved through sub-micron standard CMOS (Complementary Metal Oxide Semiconductor) technologies. The main applications are in specific cell labeling, neural activity detection, and biomedical imaging. In this paper the recent research studies on implantable CMOS image sensors for neural activity monitoring of brain are being quantified and reviewed. Based on the results, the suitable implantable image sensors for brain neural monitoring should have high signal to noise ratio of above 60 dB, high dynamic range of near 88 dB and low power consumption than the safety threshold of 4W/cm2. Moreover, it is found out that the next generation of implantable imaging device trend should reduce the pixel size and power consumption of CMOS image sensors to increase spatial resolution of sample images.

New Compact Electron Cyclotron Resonance Plasma Source for Silicon Nitride Film Formation in Minimal Fab System

A compact magnetic-mirror confined electron cyclotron resonance plasma source for low-damage plasma processings was developed, especially aiming for the realization of high-quality silicon nitride film formation for the sub-micron complementary metal-oxide semiconductor device processes in the minimal fab system. The developed plasma source was installed in the minimal tool, and deposition of silicon nitride film was performed. The magnetic mirror confinement method worked well to excite the high-density plasma with low plasma excitation power of 10 W or less. By adopting the substrate position slightly apart from the core plasma region with the pressure range of 25 Pa, the silicon nitride film having the similar N/Si ratio to the ideal value of Si3N4 could be obtained in the room-temperature deposition. Under this condition, impurity concentration of oxygen in the film could be suppressed less than 1%, which was even smaller than that in the controlled low-pressure chemical-vapor deposited film at 750 °C.

Single event upset rate modeling for ultra-deep submicron complementary metal-oxide-semiconductor devices

Based on the integral method of single event upset (SEU) rate and an improved charge collection model for ultra-deep submicron complementary metal-oxide-semiconductor (CMOS) devices, three methods of SEU rate calculation are verified and compared. The results show that the integral method and the figure of merit (FOM) methods are basically consistent at the ultra-deep submicron level. By proving the validity of the carrier collection model considering charge sharing, the applicability of two FOM methods is verified, and the trends of single-bit and multiple-bit upset rates for ultra-deep submicron CMOS are analyzed.

Dose-rate sensitivity of deep sub-micro complementary metal oxide semiconductor process

Enhancing low dose rate sensitivity (ELDRS) in bipolar device is a major problem of liner circuit radiation hardness prediction for space application. ELDRS is usually attributed to space-charge effect. A key element is the difference in transport rate between holes and protons in SiO2. Interface-trap formation at high dose rate is reduced due to positive charge buildup in the Si/SiO2 interfacial region (due to the trapping of holes and/or protons) which reduces the flow rates of subsequent holes and protons (relative to the low-dose-rate case) from the bulk of the oxide to the Si/SiO2 interface. Generally speaking, the dose rate of metal oxide semiconductor (MOS) device is time dependent when annealing of radiation-induced charge is taken into account. The degradation of MOS device induced by the low dose rate irradiation is the same as that by high dose rate when annealing of radiation-induced charge is taken into account. However, radiation response of new generation MOS device is dominated by charge buildup in shallow trench isolation (STI) rather than gate oxide as older generation device. Unlike gate oxides, which are routinely grown by thermal oxidation, field oxides are produced using a wide variety of deposition techniques. As a result, they are typically thick (100 nm), soft to ionizing radiation, and electric field is far less than that of gate oxide, which is similar to the passivation layer of bipolar device and may lead to ELDRS. Therefore, dose-rate sensitivities of n-type metal oxide semiconductor field effect transistor (NMOSFET) and static random access memory (SRAM) manufactured by 0.18 m complementary metal oxide semiconductor (CMOS) process are explored experimentally and theoretically in this paper. Radiation-induced leakages in NMOSFET and SRAM are examined each as a function of dose rate. Under the worst-case bias, the degradation of NMOSFET is more severe under the low dose rate irradiation than under the high dose rate irradiation and anneal. Moreover, radiation-induced standby current rising in SRAM is more severe under the low dose rate irradiation than under the high dose rate irradiation even when anneal is not considered. The above experimental results reveal that the dose-rate sensitivity of deep sub-micron CMOS process is not related to time-dependent effects of CMOS devices. Mathematical description of the combination between enhanced low dose-rate sensitivity and timedependent effects as applied to radiation-induced leakage in NMOSFET is developed. It has been numerically found that non time-dependent effect of deep sub-micron CMOS device arises due to the competition between enhanced low dose-rate sensitivity in bottom of STI and time-dependent effect at the top of STI. The high dose rate irradiation is overly conservative for devices used in a low dose rate environment. The test method provides an extended room temperature anneal test to allow leakage-related parameters that exceed postirradiation specifications to return to a specified range.

Through silicon via based metal-semiconductor-metal photodetector in CMOS technology

This paper proposes a novel implementation of a metal-semiconductor-metal (MSM) photodetector (PD) in 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The new design uses through silicon via metal layers, introduced in modern deep submicron CMOS technologies, as an electrode of MSM PD in order to expand the space charge region of the Schottky junction. A minimum Internal Quantum Efficiency of 98.24 % in the range of 300 nm (UV) to 1000 nm (NIR) input light at 3 V bias is achieved according to numerical simulations. The new PD shows a dark current of 83.8 fA and the 3-dB bandwidth of 41.4 GHz, at the same bias. The maximum crosstalk noise for two different types of proposed PDs is 57.73 and 0.37 %.

Impact of Total Ionizing Dose on the Data Retention of a 65 nm SONOS-Based NOR Flash

In this paper, the impact of total ionizing dose on the data retention behavior of a silicon-oxide-nitride-oxide-silicon-based NOR flash nonvolatile memory is studied for the first time on a deep sub-micron 65-nm complementary metal-oxide semiconductor technology node. The fundamental nonvolatile single-level cell memory element utilizes uniform Fowler-Nordheim (F-N) tunneling for both program and erase operations. The data retention behavior is investigated on a 4-Mb NOR Flash-based memory array at space-level total ionizing dose (TID) exposures up to 500 krad. Excessive TID exposure reduces the program-erase window but improves the thermal emission coefficient and, hence, improves data retention.

Radiation effect of deep-submicron metal-oxide-semiconductor field-effect transistor and parasitic transistor

The metal-oxide-semiconductor field-effect transistor (MOSFET) and the parasitic bipolar transistor of domestic complementary metal oxide semiconductor (CMOS) process are irradiated with 60Coγ rays to investigate the failure mechanism of the mixed-signal ICs fabricated by deep submicron CMOS process, caused by total dose radiation. The research results are as follows. 1) The parasitic sidewall and top corner regions contribute to the intra-device leakage. 2) The parasitic bipolar transistor of CMOS process is not sensitive to total dose radiation, which is very different from the conventional bipolar transistor. Preliminary analysis suggests that the difference originates from the differences in the structural and making process. 3) The total dose radiation damage to the parasitic bipolar transistors is not coupled with the damage to the NMOS transistor in the same CMOS process. 4) Based on the above study, the radiation failure mechanisms of the analog and digital module in mixed-signal ICs fabricated respectively by the domestic and commercial CMOS process are investigated. Preliminary analysis suggests that the increase of off-leakage current of MOSFET is responsible mainly for the increase in power consumption of digital module, and the insensitivity of bandgap voltage reference to total dose radiation originates from the radiation resistance of the parasitic bipolar transistor which is the important part of bandgap voltage reference in CMOS mixed-signal ICs.

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory (SRAM) cell structure when the cell is in idle mode (performs no data read/write operations) and active mode (performs data read/write operations), along with the requirements for the overall standby leakage power, active write and read powers. A comparison has been drawn with existing SRAM cell structures, the conventional 6T, PP, P4 and P3 cells. At the supply voltage, VDD = 0.8 V, a reduction of 98%, 99%, 92% and 94% is observed in the gate leakage current in comparison with the 6T, PP, P4 and P3 SRAM cells, respectively, while at VDD = 0.7 V, it is 97%, 98%, 87% and 84%. A significant reduction is also observed in the overall standby leakage power by 56%, the active write power by 44% and the active read power by 99%, compared with the conventional 6T SRAM cell at VDD = 0.8 V, with no loss in cell stability and performance with a small area penalty. The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor (CMOS) technology, tox = 2.4 nm, Vthn = 0.22 V, Vthp = 0.224 V, VDD = 0.7 V and 0.8 V, at T = 300 K.

Modelling and simulation techniques for highly integrated, low-power wireless sensor networks

The design of state-of-the-art low-power wireless sensor nodes involves the convergence of many technologies and disciplines. Submicron complementary metal oxide semiconductor (CMOS) devices, micro-electro-mechanical system filters, on- and off-chip electromagnetic elements, sensors and thin-film batteries are some of the technologies that will enable pervasive systems such as wireless sensor networks. High system complexity requires the use of many simulation environment during design: algorithm simulators, mechanical finite element analysis, behavioural and transistor-level circuit simulators, electromagnetic (EM) simulators, thin-film battery simulators and network simulators. It is shown that highly integrated, self-contained systems require multiple-domain simulations to uncover complex interactions between domains. Specific examples of block- and system-level design methodologies used in low-power wireless systems are presented here. Bottlenecks in the current methodology will be identified with an eye towards improving the scope and resolution of system-level simulations.

Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing

The increase in process parameter variations and off-state current for deep submicron complementary metal oxide semiconductor (CMOS) technologies makes conventional (single threshold) IDDQ testing ineffective. Delta IDDQ testing performed at two temperatures for a given test vector and called ‘thermal delta IDDQ testing’ is a more attractive alternative and is investigated by the authors. On the basis of statistical Monte Carlo simulations and industrial data, it is shown that lowering the temperature from 330 K to 280 K results in a more than ×100 reduction of IDDQ mean value and approximately ×15 reduction of IDDQ standard deviation of defect-free 0.18 µm CMOS circuits.

Crosstalk Effects Caused by Single Event Hits in Deep Sub-Micron CMOS Technologies

In deep sub-micron technologies, scaling and closely packed interconnects magnify crosstalk effects causing a Single Event Transient (SET) pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This paper analyses factors affecting the crosstalk pulse due to an Single Event Upset (SEU) in digital logic circuits for advanced technologies. Simulation results obtained substantiate that the effects of Single Event (SE) crosstalk increase as devices scale down, as the amount of charge deposited to cause an upset increases, and as the interconnect length increases

Monolithic Integration of Electronics and Sub-wavelength Metal Optics in Deep Submicron CMOS Technology

AbstractThe structures that can be implemented and the materials that are used in complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) technology are optimized for electronic performance. However, they are also suitable for manipulating and detecting optical signals. In this paper, we show that while CMOS scaling trends are motivated by improved electronic performance, they are also creating new opportunities for controlling and detecting optical signals at the nanometer scale. For example, in 90-nm CMOS technology the minimum feature size of metal interconnects reaches below 100 nm. This enables the design of nano-slits and nano-apertures that allow control of optical signals at sub-wavelength dimensions. The ability to engineer materials at the nanoscale even holds the promise of creating meta-materials with optical properties, which are unlike those found in the world around us. As an early example of the monolithic integration of electronics and sub-wavelength metal optics, we focus on integrated color pixels (ICPs), a novel color architecture for CMOS image sensors. Following the trend of increased integration in the field of CMOS image sensors, we recently integrated color-filtering capabilities inside image sensor pixels. Specifically, we demonstrated wavelength selectivity of sub-wavelength patterned metal layers in a 180-nm CMOS technology. To fulfill the promise of monolithic photonic integration and to design useful nanophotonic components, such as those employed in ICPs, we argue that analytical models capturing the underlying physical mechanisms of light-matter interaction are of utmost importance.

Integrated‐circuit‐pressed ceramic‐package antenna

AbstractA novel integrated‐circuit‐pressed ceramic‐package antenna is proposed for the first time. The antenna is intended for use in the single‐chip solutions of wireless transceivers using deep submicron complementary metal‐oxide semiconductor (CMOS) technology. The prototype antenna printed on a dual‐in‐line integrated‐circuit‐pressed ceramic package is comparatively studied at 2.4 GHz with and without CMOS chip loading. The results show that CMOS chip loading greatly increases the impedance bandwidth, but slightly decreases the radiation efficiency of the antenna. The loaded antenna achieves an impedance bandwidth of 15.7% and a radiation efficiency of 64 ± 4%, which are sufficient for most applications. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 42: 143–147, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20233

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Test structures consisting of shallow trench isolation (STI) structures are fabricated using advanced silicon (Si) technology. Different process parameters and geometrical features are implemented to investigate the residual mechanical stress in the structures. A technology computer aided design homemade tool, IMPACT, is upgraded and optimized to yield strain fields in deep submicron complementary metal–oxide–semiconductor devices. Residual strain in the silicon substrate is measured with micro-Raman spectroscopy (μ-RS) and/or convergent beam electron diffraction (CBED) for large (25 μm) and medium size (2 μm), while only CBED is used for deep submicron STI (0.22 μm). We propose a methodology combining CBED and technology computer aided design (TCAD) with μ-RS to assess the accuracy of the CBED measurements and TCAD calculations on the widest structures. The method is extended to measure (by CBED) and calculate (by TCAD) the strain tensor in the smallest structures, out of the reach of the μ-RS technique. The capability of determining, by both measurement and calculation, the strain field distribution in the active regions of deep submicron devices is demonstrated. In particular, it is found that for these structures an elastoplastic model for Si relaxation must be assumed.

Influence of hydrogen plasma treatment on boron implanted junctions in silicon

Alleviation of transient enhanced diffusion (TED) is a critical issue in realizing deep submicron complementary metal–oxide–semiconductor transistors. In this article we present the influence of hydrogen plasma on TED of boron, along with deep level transient spectroscopic (DLTS) studies on defect evolution as a function of anneal temperature. The studies reveal that TED monotonically increases as a function of anneal temperature up to 650 °C, where maximum TED occurs. A further increase in anneal temperature reveals TED reduction. The DLTS shows a corresponding increase in defect density up to 650 °C and then decreases when annealed at 850 °C for the same amount of time.

Improving the yield of deep submicron CMOS processes by controlling the grain size of poly-Si gate through post deposition rapid thermal anneal

The morphology of gate poly-Si was found to be critical for achieving fully functional 4-Mb SRAM dies with 0.18-/spl mu/m complementary metal-oxide-semiconductor (CMOS) process. Although the functionality of 4-Mb SRAM had been achieved with as-deposited poly-Si gate, it is highly likely that the surface roughness of the as-deposited poly-Si is a major concern for sub-0.18-/spl mu/m technology. In this report, it is shown that the small-size grains, achieved by recrystallizing as-deposited amorphous Si via rapid thermal anneal prior to gate patterning, is very effective in reducing the number of failing bits of 4-Mb SRAM dies. The conventional deposition process for gate poly-Si can therefore be adopted for fabricating sub-0.18-/spl mu/m CMOS integrated circuits.

Low-temperature formation of highly reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal–oxide–semiconductor technology

Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride was deposited on Si substrates by atomic-layer deposition (ALD) at low temperatures (&amp;lt;550 °C). Substantial enhancement of reliability was obtained with respect to the conventional SiO2 samples. An exciting feature of suppressed soft breakdown events was observed. Injected-carrier-induced physical damage, which results in the formation of the conductive filaments at the poly-Si/ALD-Si-nitride and ALD-Si-nitride/Si-substrate interfaces, is suppressed due to the higher stability of the Si–N bonds than that of the strained Si–O bonds. This suppression of physical damage leads to enhanced reliability. Therefore, the ALD silicon nitride can be a good choice for a highly reliable ultrathin gate dielectric in deep submicron complementary metal–oxide–semiconductor technology.