A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced [All rights reserved – Patents Pending]. This novel design solution can be implemented straightforwardly without process modifications. ESD performance levels obtained in different 0.25 and 0.18 μm CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economic silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide-blocked designs (Patents Pending) is presented.