A pixel readout chip for 10-30 MRad in standard 0.25 /spl mu/m CMOS

Abstract

A radiation tolerant pixel detector readout chip has been developed in a commercial 0.25 /spl mu/m CMOS process. The chip is a matrix of two columns of 65 identical cells. Each readout cell comprises a preamplifier, a shaper filter, a discriminator, a delay line and readout logic. The chip occupies 10 mm/sup 2/, and contains about 50000 transistors. Electronic noise (/spl sim/220 e rms) and threshold dispersion (/spl sim/160 e rms) allow operation at 1500 e average threshold. The radiation tolerance of this mixed mode analog-digital circuit has been enhanced by designing NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The chip, which was developed at CERN for the ALICE and LHCb experiments, was still operational after receiving 3.6/spl times/10/sup 13/ protons over an area of 2/spl times/2 mm. Other chips were irradiated with X-rays and remained fully functional up to 30 Mrad (SiO/sub 2/) with only minor changes in analog parameters. These results indicate that careful use of deep submicron CMOS technologies can lead to circuits with high radiation tolerance.