Submicrometer MOSFETs Research Articles

Improved hot-carrier immunity in submicrometer MOSFETs with reoxidized nitrided oxides prepared by rapid thermal processing

The fabrication of 0.8- mu m MOSFETs using 7.7-nm-thick nitrided oxides reoxidized by rapid thermal processing at 900-1150 degrees C for 15-200 s is described. The hot-carrier-induced degradation was studied in terms of subthreshold swing, threshold voltage V/sub T/, and transconductance g/sub m/ voltage characteristics. Results indicate that rapid reoxidation markedly improves hot-carrier immunity; lifetimes reaching 30-mV V/sub T/ shift and 10 percent g/sub m/ degradation are improved by 3 and 1.5 orders of magnitude compared with those for thermal oxides, respectively. A degradation characteristic inherent to the (reoxidized) nitrided-oxide system is found, based on the gate-voltage dependence of g/sub m/ degradation. >

Design methodology and size limitations of submicrometer MOSFETs for DRAM application

A design methodology of submicrometer MOSFETs for a one-transistor DRAM cell is proposed, taking into account physical limiting phenomena such as (1) avalanche breakdown at the drain junction, (2) bulk punchthrough, (3) short-channel effect, and (4) hot-electron effect, and circuit-performance requirements such as (5) leakage current, (6) access delay, (7) noise margin and (8) alpha -particle-induced soft error. It has been found that a minimum metallurgical channel length is 0.42 mu m at a circuit voltage of 2.8 V for a planar cell structure. Although these parameters are derived assuming a planar cell, the presented design method can be applied to advanced cell structures, such as stacked and trench cell structures, by setting adjustable design parameters for the area and capacitor factors of a memory cell.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A mobility model for submicrometer MOSFET simulations including hot-carrier-induced device degradation

The model presented includes the quantum effects of electrons in the inversion layer proposed by S.A. Schwarz and S.E. Russek (1983) and the surface scattering effects due to the interfacial charges. By comparison with experimental data from scaled MOSFETs, the limitation of K. Yamaguchi's (1983) mobility model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. In addition, it is shown that the modeling of the screening effect of Coulomb scattering plays an important role in simulating the hot-carrier-induced MOSFET degradation. The model can predict the current-voltage characteristics within 5% accuracy for scaled MOSFETs down to 0.5- mu m, as well as the degradation of electrical characteristics due to hot-carrier effects for submicrometer MOSFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A three-piece model of channel length modulation in submicrometer MOSFETs

A simple model for the linear region of submicrometer n-channel MOSFETs is proposed in which the effective channel length of the device is considered as a function of applied gate and drain voltages, channel doping and temperature. The MOSFET channel is supposed to have three regions with different values of surface state density and oxide charge to take into account the processing-induced damages at its edges. The model is compared with the experimental results on device transconductance at room and low temperatures. It allows an easy understanding of various results unaccounted for by standard models and offers a physical basis for more sophisticated modelling.

Punchthrough current for submicrometer MOSFETs in CMOS VLSI

Simulated and measured data show that drain-induced barrier lowering (DIBL) in buried-channel MOSFETs is different from that in surface channel (SC) MOSFETs. This is explained by the differences between channel current paths and channel potential distribution. A new parameter, defined as the incremental voltage that the drain can sustain before the punchthrough current increases by an order of magnitude, is used to indicate the rate of increase of punchthrough current and is a measure of DIBL.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The influence of tilted source-drain implants on high-field effects in submicrometer MOSFETs

Asymmetries in MOSFET high-field effects, such as impact ionization and bipolar snapback, are used to examine the influence of tilted source-drain implants on device reliability. Several process variables, including source-drain implant conditions and anneal time, are varied to determine how they affect these asymmetries. Using two-dimensional process and devices simulations to explain the physical origins of these effects, the lightly doped drain (LDD) structure is shown to offer some immunity to tilt-angle-induced reliability problems. These results are used to suggest guidelines for the design of the LDD structure. >

Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI

The gate-drain overlapped device (GOLD) structure is proposed to achieve high reliability and high performance in deep submicrometer MOSFETs. The GOLD device concept is different from that of drain-engineering methods such as the double-diffused drain (DDD) and lightly doped drain (LDD). GOLD eliminates the tradeoff between transconductance and breakdown voltage (hot-carrier, drain sustaining). The overlap effect of the GOLD devices is discussed using simulation and experiment. GOLD has a gate structure using a native oxide film (5-10 A) to obtain an overlapped fine structure. The process is also compatible with conventional LDD processes and is suitable for 0.3-0.5- mu m-design-rule devices at 5-V operation, and 3-V operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A hot-carrier analysis of submicrometer MOSFET's

Based on Monte Carlo (MC) device simulations, an analysis of hot-carrier effects in submicrometer n-MOSFETs is presented that provides detailed insight because the high-energy electrons are treated directly. The DC stress characteristics of both lightly-doped drain (LDD) and conventional As source/drain devices are found to correlate with the surface hot-electron concentration, and agreement with experimental data shows that the electron flux above 3 eV, integrated along the channel, can be used to predict device degradation. The simulations indicate that the whole DC stress characteristic can be attributed to hot electrons, while the holes generated by impact ionization have a very small probability of gaining enough energy to be injected over the oxide barrier.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VIB-3 accurate analysis of impact ionization effects in submicrometer MOSFET devices

VIB-3 accurate analysis of impact ionization effects in submicrometer MOSFET devices

A mobility model for submicrometer MOSFET device simulations

This paper describes a mobility model for submicrometer MOSFET device simulations. The model includes the quantum effects of electrons in the inversion layer proposed by Schwarz et al. By comparison with experimental data from scaled MOSFET's, the limitation of Yamaguchi's model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. This model can predict the current-voltage characteristics within 5- percent accuracy for scaled MOSFET's down to 0.5 µm.

High-frequency noise measurements on FET's with small dimensions

A low-noise high-frequency transresistance amplifier has been used to accurately measure broad-band noise in MOSFET's with small widths and submicrometer channel lengths. The technique allows noise characterization up to frequencies of 100 MHz of the small devices available as process test arrays from different fabrication lines. The noise in the different portions of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> characteristics of submicrometer MOSFET's has been characterized and shown to be greater by factors of 2 to 4 than the noise expected from long-channel noise theory.

Scaling issues related to high field phenomena in submicrometer MOSFET's

Both enhancement and depletion n-channel MOS devices with electrical channel lengths between 1 and 0.3 µm are characterized in terms of carrier heating effects. The effect of gate oxide thickness on the two-dimensional (2-D) electric field distribution has been analyzed through 2-D numerical device simulation, and its impact on carrier heating process has been experimentally quantified. Our results allow some conclusions for reduced supply voltages (2 and 3 V for temperatures of 77 and 300 K, respectively) for future NMOS technologies with design rules of 0.75 µm.

Hot-carrier generation in submicrometer VLSI environment

Submicrometer MOSFETs may suffer from reliability degradation, which has a strong correlation with substrate current. In order to know what is happening to substrate current in a VLSI environment, a substrate-current circuit simulator is developed. The simulator is applied to MOS unit circuit blocks, VLSI static memories, and dynamic memories, and their hot-carrier duty ratios are calculated. A new circuit technology, called normally-on enhancement MOSFET insertion (NOEMI), is proposed which can suppress hot-carrier generation. Several design implications for submicrometer VLSIs are obtained through the analysis.

Elimination of Subboundaries in 0.5-µm-Thick Si-on-Insulator Films Produced by ZMR

AbstractWhen Si-on-insulator films 0.3 to 0.5 µm thick are recrystallized by zone melting under the usual conditions, the defect trails within grains are subboundaries. We report that the use of an entrainment pattern, consisting of a grating of carbonized photoresist on top of the SiO2 encapsulating layer, can lead to the replacement of subboundaries by defect trails that are spaced dislocation clusters or discrete threading dislocations. Such defects are expected to be less detrimental to submicrometer MOSFET circuits than subboundaries.

A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design.

IIIB-1 Performance deviation of submicrometer MOSFET's from scaling laws

IIIB-1 Performance deviation of submicrometer MOSFET's from scaling laws

High-accuracy physical modeling of submicrometer MOSFET's

When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.

Hot-carrier effects in submicrometre MOS VLSIs

Hot-carrier effects in submicrometre MOS VLSI circuits are described in terms of (a) the hot-carrier injection mechanisms, (b) the device degradation, (c) the hot-carrier resistant device structures and (d) the hot-carrier phenomena under a bias of less than 3 V. Two significant hot-carrier injection mechanisms are proposed which are different from those of the channel hot-electron (CHE) and substrate hot-electron (SHE) injection as previously reported by Ning et al. They are (i) drain avalanche hot-carrier (DAHC) and (ii) secondarily generated hot-electron (SGHE) injection. Based on an experimental comparison of gate currents due to these mechanisms it is shown that DAHC imposes the most severe constraint on VLSI design. In addition, hot-carrier resistant device structures, such as an As-P double diffused drain (DDD) and lightly doped drain (LDD), are also described as so called ‘drain engineering techniques’ to enhance reliability of MOS devices. Finally, in anticipation of a possible reduction in power supply voltages in the future, hot-carrier phenomena have been investigated at bias levels below 3 V, where hot carriers cannot obtain enough energy to surmount the Si-SiO2 barrier. The experimental results clearly show that device degradation due to hot-carrier injection occurs even at VD &lt; 3 V. Thus, hot carrier effects remain one of the most stringent limiting factors affecting submicrometre MOSFETs, even after the power supply voltage is reduced.

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical value <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W_{\min}</tex> which is about 1 µm for 200-A gate oxide 7000-A field oxide and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 \times 10^{16}</tex> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.

IIA-3 experimental electrical characteristics of submicrometer MOSFETs

IIA-3 experimental electrical characteristics of submicrometer MOSFETs